- Design and develop deep sub-micron foundation IP circuits including standard cells, memory and customization cells for chip PPA optimization.
- Guide layout designer, assist in layout optimization based on post-layout simulation results.
- Characterize and generate design models supporting major EDA design flows including verilog, Synopsys liberty model etc.
- Design test chip testing circuits for STD/MEM/IO libraries and assist in testing.
- Minimum MS degree in EE or related majors, work experience and rank are not limited.
- Knowledge and project experience on circuit design with strong background on device physics.
- Familiar and hands-on experience in script language and behavior model, ie, Tcl, Perl, Verilog, etc. Experiences on Cadence/Synopsys/Mentor’s EDA tools.
- Self motivated, good communication and team work skills are a must.
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