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DFT Implementation lead

DFT Implementation lead
by Admin on 02-09-2023 at 2:05 pm

Website Alphawave Semi

Alphawave Semi is a design industry-leading, high-speed connectivity solutions for customers in high-growth end markets.

  • Data centre
  • AI
  • 5G wireless infrastructure
  • Data networking
  • Autonomous vehicles
  • Solid-state storage

Our leading-edge technology advances push the boundaries of wired connectivity capabilities, enabling data to travel faster, more reliably, and using lower power.

Powering next-generation technologies, we serve Tier-One customers in North America, Asia Pacific, Europe, and the UK. Our innovative solutions have repeatedly set industry benchmarks in terms of performance, power consumption, size, and flexibility.

We are looking for a DFT lead for our various high-speed interface IPs that we design in-house. These IPs are on the bleeding edge with high-speed IOs (up to 20Gbps per IO) and some of these IPs like HBM PHY and D2D PHY are completely embedded within the package i.e., they do not come out on the package balls and utilize 2.5D packaging technology. For this kind of IPs, the DFT strategy is completely different from what a regular SOC requires since it needs to target KGD binning. We are looking for a DFT lead who can help us define and implement a comprehensive DFT strategy for these IPs.


  • 6 -10 years of Experience in defining and implementing the DFT strategy for at least 2 hard IPs. For Ex. Serdes or DDR3/4/5 PHY.
  • Good in Verilog coding for synthesis and testbenches.
  • Experience in generating all the collaterals required for the customer who will be using these
  • IPs in their SOC, must understand IJTAG, SCAN, ATPG, JTAG, BSCAN concepts.
  • Ability to define the RTL requirements and DFT aware design lib elements required to make the design DFT compatible.
  • Test mode timing support, debug and closure.
  • Experience in ATE support and debug.
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To view the job application please visit

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