DFT Engineer

Experience: 3+ years
Education: Bachelor’s degree in Engineering

Roles and responsibilities:

• Scan Implementation for large SoC
• MBIST implementation
• ATPG for different fault model and gate level simulation with and w/o SDF
• Understand DFT architecture and able to solve the issues of DFT
• DFX design front-end checks, Spyglass check, CDC checks
• Timing closure support for DFT Test Mode
• Silicon bring-up support and debugging Silicon failures

Any special or skills related notes:

• Hands on experience with Cadence Scan and ATPG tool – Genus and Modus
• Synopsys SMS tool knowledge for MBIST
• iJTAG and IEEE1500 wrapper understanding.

Skills:

• Scan and ATPG (Cadence – Genus and Modus tool)
• MBIST
• Spyglass
• Silicon Debug

We would like to know following.

• Total numbers of years’ experience
• Most recent use year/project