Design Verification Engineer
As a Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results.
This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works. What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.
Responsibilities
- Review and influence product definition and specifications from a verification perspective
- Architect and design debug and verification hooks as needed
- Select the best tools and methods for verification
- Help to prioritize the verification work efforts
- Brainstorm and drive solutions across disciplines to improve product quality and engineering productivity
Requirements
- A minimum of 3 years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.)
- Familiarity with and/or ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.)
- A conscientious and thorough approach to Design Verification
- Solid understanding of processor and SoC architecture, or a strong desire and ability to learn same
- A passion for verification as a long term career path
- Good interpersonal skills to listen to diverse points of view and influence people from different disciplines
- An unwavering commitment to product quality
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