Design Rule Architecture / Path Finding Eng (SK)

Job Description

This is an exciting time to be at Intel!  Come join Intel® 3D NAND Technology and Manufacturing (NAND-DTM) Group as a Product Development Engineer and work on one of the most advanced 3DNAND and SSD technology portfolios in the world.   As a global leader in the semiconductor industry, Intel possesses many industry leading SSD technologies including the most capable Quadruple Level Cell QLC Intel® 3D NAND Technology Flash products.

Non Volatile Memory Device and Integration engineers are responsible for leading research and development in order to architect, develop and deliver leading edge nonvolatile memory technologies to high volume manufacturing. They contribute to defining process and device architectures, technology collaterals as well as develop scaling paths for leading edge memory technologies. The scope includes development of new types of process and device architectures involving novel materials, structures and integration schemes to deliver industry leadership in density, performance, reliability and cost. They collaborate with technology development partners in defining goals, developing the vision, aligning strategy and driving fast paced silicon development to meet aggressive technology node cadences. In addition they work closely with the product and system teams to ensure seamless integration of the memory components into Intel’s system products as well as with the manufacturing Fabs to ensure a seamless technology transfer and ramp to support the full envelope of component and system products.

This particular role responsibilities include:

Architecture /Path finding activities to define and enable next generation memory technologies

Architect design rules ( Physical design rules, Electrical design rules, CMOS , array ) to enable best in class die size

Interact and lead cross functional groups in TD, design, DA, Rel to define path finding activities including test chip definitions, lead vehicle definitions and understand and support volume ramp

Develop and maintain design rule document by having various interactions with process integration, die design, scribe design and CMOS and array device groups.

Use DF2, Cadence, K2View, Vcats, to develop and debug the rules.

Interact with CAD to debug the rules and come up with sanity checks to understand the interaction with various mask and base layers.

Help in updating the logic of the generators by studying the sizing tables and Calibre code.

Help in generating the Calibre code for the various sanity checks.

Perform DRC checks, layout vs. schematic and netlist extraction tools to ensure correctness in layout and also help in scribe test structures.

Interface with multiple other groups like Process Integration, Design Rules, CAD, Layout, Scribe and Mask shops with patience and thoroughness.

Drive diagnostic projects across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask synthesized data.

This position is in the NAND-DTM Group which is aligned to phase 2 of the sale of the Intel® 3D NAND Technology business to Solidigm, a wholly owned subsidiary of SK Hynix. Employees in this business group will work on developing Intel® 3D NAND Technology and components.  Phase 2 of the transaction is expected to close in March 2025 at which time employees aligned to this phase of the transaction will transition employment to Solidigm.  Solidigm, a leading global supplier of Intel® 3D NAND Technology flash memory solutions, is headquartered in San Jose, California with offices worldwide.

Qualifications

Minimum Qualifications:

• Master’s degree in Electrical Engineering. Chemical Engineering, Computer Science or related discipline
• 5 years of experience in Memory Design and architecture, Process architecture , Device development, Physical design and verification sig offs
• 5 years of Design rules ( Physical, electrical) and silicon architecture experience.
• 5 years of experience with CAD tools , methodology and software, in particular DF2, Schematic and layout, K2view and Calibre.

  Preferred skills and experience:

• Semiconductor device and design architecture
• Design methodology including Design Rule , Schematic (DRC/LVS), can fix most design and DRC/LVS issues that come up; work with the LVS/DRC maintenance group to build new models as needed.
• Experience with generators and how they are related to process is helpful to fix any DRC/LVS issues..
• Experience with device physics and parametric analysis.
• Experience with photolithography and reticle creation.
• Tape-out, OPC and Mask Generation Flows for High volume manufacturing.
• GDS2/SF/OASIS format and layout hierarchy and layer maps.
• DFII, K2VIEW and other Industry standard CD capture/measurement tools.