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Back End Design Engineer

Back End Design Engineer
by Admin on 11-21-2022 at 12:23 pm

Website Verisilicon

Descriptions

  • Responsible for SDC and UPF/CPF development and debug.
  • Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation.
  • IP level and chip level physical verification and DFM rule checking.
  • Power analysis and IR drop/EM analysis for both static and dynamic.
  • Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process.
  • Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure.
  • Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns.
  • Communicate with customer as well as AE or sales.

Requirements

  • Bachelor’s degree or above in EE, work experience and rank are not limited.
  • Skilled in csh/perl/tcl.
  • 2+ years work experience in relevant areas is required for Senior Engineer position; Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification.
  • Rich experience on timing/noise violation fixing and CTS tree synthesis.
  • Good understanding about entire development flow of IC design.
  • Good understanding about FE design, process, package, testing, etc.
  • Fluent in both English and Chinese.
  • Self motivated, good communication skill and team work spirit.
Apply for job

To view the job application please visit www.verisilicon.com.

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