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ASIC Digital Design Engineer

ASIC Digital Design Engineer
by Admin on 04-26-2022 at 1:28 pm

  • Full Time
  • Canada
  • Applications have closed

Website Synopsys

Job Description and Requirements

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

ASIC Design Engineer

Seeking a highly motivated and innovative ASIC Design Engineer with theoretical and practical background in high-speed data recovery circuits.

Working as part of a highly experienced mixed-signal design team, you will be involved in verifying current and next generation products.

This is an excellent opportunity to work with an expert team of digital and mixed signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips.

Responsibilities will include:

  • ASIC, FPGA and Firmware design and verification;
  • reviewing digital and analog specification;
  • creating analog model based on schematic and analog function;
  • writing modular constrained-random verilog and system-verilog testbenches;
  • performing functional coverage;
  • assertion coverage, and code coverage;
  • creating and tracking testplans;
  • reviewing failure cases;
  • running gate-level simulations.

Requirements:

  • You have preferred BSEE
  • Must have experience in ASIC design, synthesis, CDC…
  • Must have hands-on experience in writing complex testcases in Verilog and System Verilog,
  • Must have familiarity with code quality metrics.
  • Ability to create specification for system level overview of digital and analog
  • Knowledge of the following:
    • high-speed digital & mixed-signal design
    • asynchronous clock crossings
    • DFT design methodologies
  • good organization and communication skills
  • interaction with different design groups and customer support teams.
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