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Design Verification Engineer

Design Verification Engineer
by Daniel Nenni on 09-08-2020 at 6:30 pm

Website ArterisIP

As a Design Verification Engineer at Arteris, you will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll go home at the end of the day amazed at all the places where your creations end up. You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.


Advanced UVM based test bench development and debugging
Defining, documenting, developing and executing RTL verification test/coverage at system level
Performance verification and power-aware verification
Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
Help improve and refine verification process, methodology, and metrics
UVM expertise on complex SoC projects from test bench development to verification closure
Experience, Requirements and Qualifications:

1 or more years of design and verification experience and a plus in interconnect verification experience
Experience with Cadence, Synopsys, Mentor logic simulators
Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript

BS degree or higher in Engineering or Computer Science

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