TSMC's 1.4nm process timeline accelerates, with mass production happening sooner than expected

[Daniel Nenni]

TSMC is building new facilities for its next-generation 1.4nm process and construction is ahead of schedule, accelerating the timeline for mass production.

TSMC is building a 1.4nm/A14 plant in Taichung's CTSP, ahead of schedule, with phase one due April 2027. Trial runs could start Q3 2027 and mass production by mid-2028. The $49 billion facility will use 2nd‑gen GAAFETs (NanoFlex Pro) with current EUV; projected density and efficiency gains noted.

For its next-generation 1.4nm process, TSMC is currently constructing a new 1.4nm advanced process plant as part of the company's expansion. According to a new report via Taiwan's Commercial Times, construction of this new plant is currently ahead of schedule, with the first manufacturing phase of the expansion set to be completed by April 2027.

Of course, this doesn't mean that production for TSMC's 1.4nm process or A14 node will commence right away, but if the April 2027 timeline holds, the first trial production run could kick off as early as Q3 2027. Again, assuming there aren't any unforeseen delays or hiccups, this would then lead to mass production beginning by mid-2028.

Located in the Taichung Phase II Park of the Central Taiwan Science Park (CTSP), the location's Administration Director Hsu Mao-hsin has confirmed that the faster-than-expected progress included the use of AI for image recognition and the development of safety systems, with VR simulations also leveraged for safety training for the cutting-edge facility.

Construction for the dedicated A14 facility began in November 2025, with an estimated investment of $49 billion. The technology is said to leverage second-generation Gate-All-Around Field-Effect Transistors (GAAFETs) with TSMC's NanoFlex Pro architecture. Interestingly, it will not make use of the newer High-NA EUV lithography, but instead stick with TSMC's current EUV technology.

As for TSMC's next-generation A14 process node, compared to the current flagship N2 3nm process, it's expected to deliver a 20% increase in logic density, 15% higher speeds at the same power level, and up to 30% more power efficiency when using the same frequency.

Read more: https://www.tweaktown.com/news/1129...ion-happening-sooner-than-expected/index.html

 

[Daniel Nenni]

TSMC Technology Symposium 2026 Overview - Semiwiki

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[lefty]

this would then lead to mass production beginning by mid-2028.

Wasn't this already the schedule? It says on TSMC web page "A14 production is on track for 2028."

 

[Daniel Nenni]

Wasn't this already the schedule? It says on TSMC web page "A14 production is on track for 2028."

Exactly........

 

[my_wing]

Please provide us with a customer list of A16 node first before even try to push for A14.

Oh wait, is that now it is gearing up another name changes the old A16 is now A14.

 

[Daniel Nenni]

Please provide us with a customer list of A16 node first before even try to push for A14.

Oh wait, is that now it is gearing up another name changes the old A16 is now A14.

Nvidia is the one I am aware of. They co developed it so that makes sense. I thought AMD would jump aboard but I have not seen it. Maybe some of the big AI chip people? We probably will not hear about it until next year's Tech Forum.

 

[hist78]

Please provide us with a customer list of A16 node first before even try to push for A14.

Oh wait, is that now it is gearing up another name changes the old A16 is now A14.

Nvidia is the one I am aware of. They co developed it so that makes sense. I thought AMD would jump aboard but I have not seen it. Maybe some of the big AI chip people? We probably will not hear about it until next year's Tech Forum.

TSMC’s A16 and A14 target different customer needs and follow different timeline considerations. Both have been listed in TSMC’s roadmap for quite some time. I don’t believe that “the old A16 is now A14”.

Based on the N2 family process nodes, TSMC’s A16 adds backside power delivery along with additional power and performance improvements. It is better suited for high performance computing workloads, such as Nvidia’s AI related chip designs. That’s why Nvidia takes A16, while Apple may skip it. TSMC plans to begin A16 high volume manufacturing (HVM) in 2027. As a market leader facing intense competition, Nvidia must take every opportunity to extend its lead over competitors.

A14 represents a generational shift and is initially aimed at the mobile and consumer markets. If everything proceeds smoothly, A14 will enter HVM in 2028. This difference in market focus is why we currently see more activity around A14 than A16.

If a customer’s order is large enough, with the right price and the right market conditions, TSMC will create a process node for a few customers or even for a single customer. Apple’s A8 SoC, which was the only major customer on TSMC’s 20nm node, is a perfect example.

TSMC’s high tool conversion rate between nodes (for example, N5 to N3 at roughly 85%–90%) also enables this “one or few customers” practice. High reuse of equipment makes it economically viable for TSMC to support a specialized node even if only a small number of customers (but high volume) adopt it.

 

[my_wing]

TSMC’s A16 and A14 target different customer needs and follow different timeline considerations. Both have been listed in TSMC’s roadmap for quite some time. I don’t believe that “the old A16 is now A14”.

Based on the N2 family process nodes, TSMC’s A16 adds backside power delivery along with additional power and performance improvements. It is better suited for high performance computing workloads, such as Nvidia’s AI related chip designs. That’s why Nvidia takes A16, while Apple may skip it. TSMC plans to begin A16 high volume manufacturing (HVM) in 2027. As a market leader facing intense competition, Nvidia must take every opportunity to extend its lead over competitors.

A14 represents a generational shift and is initially aimed at the mobile and consumer markets. If everything proceeds smoothly, A14 will enter HVM in 2028. This difference in market focus is why we currently see more activity around A14 than A16.

If a customer’s order is large enough, with the right price and the right market conditions, TSMC will create a process node for a few customers or even for a single customer. Apple’s A8 SoC, which was the only major customer on TSMC’s 20nm node, is a perfect example.

TSMC’s high tool conversion rate between nodes (for example, N5 to N3 at roughly 85%–90%) also enables this “one or few customers” practice. High reuse of equipment makes it economically viable for TSMC to support a specialized node even if only a small number of customers (but high volume) adopt it.

There is no different expect a bit of node optimisation from TSMC for A16 and A14

The current A16 is the old and renamed version of N2P.

A14 has shift nothing, the only thing is shift is because TSMC needed to face the fact, the fact that Panther Lake and Clearwater Forest which is on 18A can run well, i.e. both Mobile and Server (believe me there are tons of customer i.e. Nokia and Ericsson going to build VRAN system for Vodafone, Verizon, etc. So that BSPD is not for Server or HPC only, it has been proven and TSMC has to shift, Vs Fact, can't market against a Fact that is openly available on the market.

After I have the time and look at the VLSI TSMC paper, my take is as follows:

BSPD types:
A) Although the power is sourced from the back, the transistor still obtain its power from M0 layer.
B) Also known as Via, PowerVia, Hybrid (there is a lot of names), Power is source from the back, transistor obtain its power on the same layer as the transistor, a Power Hub is build on the transistor layer to power the transistors around.
C) Also Known as Direct, Power is source from the back and transistor obtain its power from the Backside layer, in my created term Backside M0 Layer.

The photo on TSMC VLSI paper can clearly see the 3 GAA layers, and the EPI is from the side i.e. the transistor layer.

TSMC marketing team can be creative and name whether they like, but without further proof that I am clearly wrong, I am going to say TSMC A16 is currently implementing opinion B of the above, i.e. the same technology which is used by PowerVIA at 18A, there is nothing advance in TSMC A16/N2/N2P, they all technology that is widely available in the form of 18A and Panther Lake.

One thing that 18A is already shown to be innovative:
As per my previous statements, I mentioned BSPD is not increase any heat issues, it is created because the transistor is now packing denser, and how to take heat out from the chip depends on material use and shape of the chip (internal shape), it is now known that Intel had developed a material that use the vacated copper line and improve the overall thermal transfer, that is why during Pat time (can't remember a source), he ask EDA tools maker to focus on 18A as well they needed a solution that help designer not only to layout the wire, but help to design an "internal heat sink" that can drive the heat out of the transistor / chip as a whole.

Intel Foundry Details Process Milestones and Future Innovation at VLSI Symposium

Intel 18 A-P now in risk production with higher performance, enhanced thermal characteristics and design rule compatibility with Intel 18A

newsroom.intel.com

If TSMC is serious about making to the top again, please do some tech work, not going into financial and hope for the best.