TSMC A16 backside power at 2026-Jun-VLSI

[NY_Sam2]

TSMC A16 backside power at 2026-Jun-VLSI
. no (major) surprise, just details, messages for (mostly) Customers
. (not for all but) for AI/HPC Customers (with liquid cooling)
. (not PowerVia but) Backside Direct Contact
. Vmin -70mV thanks to backside power
. temperature sensor from BJT to BEOL Resistor, a change due to ultra-thin substrate
. more slides at link = https://ascii.jp/elem/000/004/413/4413973/2/

 

[IanD]

TSMC A16 backside power at 2026-Jun-VLSI
. no (major) surprise, just details, messages for (mostly) Customers
. (not for all but) for AI/HPC Customers (with liquid cooling)
. (not PowerVia but) Backside Direct Contact
. Vmin -70mV thanks to backside power
. temperature sensor from BJT to BEOL Resistor, a change due to ultra-thin substrate
. more slides at link = https://ascii.jp/elem/000/004/413/4413973/2/
View attachment 4832

And just to be crystal clear, that speed increase/Vdd decrease only applies to high-power chips with a dense power grid (hence the AI/HPC customers comment), for many devices (e.g. mobile) it's much smaller than that. Also note that the super-3D MIM is also now available in N2P, not just A16.

 

[Daniel Nenni]

Nvidia co developed this so they will use it for sure. Not aware of anybody else yet. Maybe AMD.

 

[RFletch]

The technology looks very promising. But, the real challenge will be manufacturing complexity, wafer thinning control, backside alignment accuracy, and yield learning.

The practical application will decide the final advantage.

 

[IanD]

The technology looks very promising. But, the real challenge will be manufacturing complexity, wafer thinning control, backside alignment accuracy, and yield learning.

The practical application will decide the final advantage.

Correct -- but even if all the manufacturing issues are resolved (which I assume they will be, TSMC are the best on the planet at this) it will still come down to the pros vs. cons for each product/project -- including PPA, thermals, wafer cost, library/IP availability, design/learning curve for BSPD.

Designs which are high-power-density and actively cooled (HPC/AI) and where ultimate PPA matters more than cost will use BSPD -- Nvidia are a perfect example.

Designs which are lower-power-density and not actively cooled and where cost matters more than ultimate PPA will continue to use FSPD -- I expect most mobile devices will fall into this category, indeed most non-AI/HPC chips.

There are not many designs (and from only a few customers) that fall into the first category but they do tend to be huge chips made in high volumes -- so that's a lot of BSPD wafers.

There are a huge number of designs (and from a lot of customers) that fall into the second category, which tend to be smaller chips, some of which are also huge volumes -- so that's a lot of FSPD wafers.

It's not obvious which "lot" is bigger -- in wafer volume it may turn out to be AI/HPC (at least, until the AI bubble bursts), but in turns of design effort and number of design starts FSPD is going to dominate for a long time -- and this is what most chip designers will find themselves working on, not the handful of "industry-leading" BSPD chips.

 

[Daniel Nenni]

The technology looks very promising. But, the real challenge will be manufacturing complexity, wafer thinning control, backside alignment accuracy, and yield learning.

The practical application will decide the final advantage.

I just got the VLSI Conference paper on this by TSMC. Will get something up this week. Very interesting.

 

[my_wing]

TSMC A16 backside power at 2026-Jun-VLSI
. no (major) surprise, just details, messages for (mostly) Customers
. (not for all but) for AI/HPC Customers (with liquid cooling)
. (not PowerVia but) Backside Direct Contact
. Vmin -70mV thanks to backside power
. temperature sensor from BJT to BEOL Resistor, a change due to ultra-thin substrate
. more slides at link = https://ascii.jp/elem/000/004/413/4413973/2/

View attachment 4832

. (not PowerVia but) Backside Direct Contact

For all the good and knowledgeable person out there, I have a question, in short, I see this as a PowerVIA setup not Backside Direct Contact.

1) The EPI on the presentation is next to those "GAA" looking layers, 3 GAA layer, really really matched.
2) If the GAA layer is not directly above the EPI, it is not Backside Direct Contact, it is PowerVIA.
3) Don't let the marketing name fool you, there was clear presentation by Applied Materials, this to me is the VIA approach.

Any comments welcome, just need some understanding

 

[Daniel Nenni]

TSMC A16 Backside Power at VLSI 2026 - Semiwiki

TSMC’s A16 technology, presented as Paper T1.5 at the June 2026 IEEE/JSAP VLSI Symposium, marks the company’s first angstrom-class CMOS platform combining enhanced nanosheet gate-all-around transistors with backside power delivery. The key integration feature is Super Power Rail, or SPR, which...

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