Samsung’s 3D-Memory Roadmap Reshapes AI Computing

[Daniel Nenni]

Samsung Electronics has set out an ambitious 3D-memory roadmap designed to strengthen its position in the fast-growing market for artificial-intelligence infrastructure. Unveiled at the Future of Memory and Storage 2026 conference, the strategy centers on bringing memory physically closer to AI accelerators, increasing bandwidth while cutting energy use and data-transfer delays.

Its headline concept, zHBM, places high-bandwidth memory directly above an accelerator instead of beside it. Samsung says a future zHBM interface could deliver roughly eight times the performance of HBM5, more than ten times its memory density, threefold better energy efficiency, and over 50% lower thermal resistance. The design could also incorporate customer-specific intellectual property between the memory and processor, supporting more specialized AI systems.

Samsung also introduced zNAND-O, a four- or eight-layer NAND architecture aimed at edge AI, where low latency and efficient local processing are critical. More immediately, its V10 Bonding V-NAND prototype uses wafer bonding and exceeds 400 layers. The company claims it raises density by about 58% over V9 while improving read, write, and input/output performance.

The roadmap extends across HBM4E, HBM5, processing-in-memory LPDDR5X, and enterprise storage, reflecting Samsung’s effort to offer an integrated stack spanning memory, foundry, and advanced packaging. For AI technology leaders, the significance is architectural: model performance increasingly depends not only on faster processors, but on reducing the cost, heat, and latency of moving data. Samsung’s concepts remain forward-looking, so customer qualification, manufacturing yield, thermals, pricing, and delivery schedules will determine whether the roadmap becomes a competitive advantage at scale.

https://www.bloomberg.com/news/articles/2026-08-04/samsung-reveals-new-3d-memory-roadmap-in-bid-for-ai-tech-lead

 

[Fred Chen]

The zHBM looks like exactly what d-Matrix did here: https://ramyadhadidi.github.io/files/dMatrix-Raptor-ISCA.pdf. They had to do a DRAM re-design, banks and all. The real mystery is who made this DRAM and stacked it on their logic die from TSMC.

 

[hist78]

The zHBM looks like exactly what d-Matrix did here: https://ramyadhadidi.github.io/files/dMatrix-Raptor-ISCA.pdf. They had to do a DRAM re-design, banks and all. The real mystery is who made this DRAM and stacked it on their logic die from TSMC.

With the advancement of AI and advanced packaging, the power to define standards and requirements has increasingly shifted to the foundries.

Samsung is an IDM that also serves external foundry customers, and it naturally wants to play a bigger role in defining standards and technology approaches that support its logic design, foundry, memory, and device businesses. But Samsung also faces a classic IDM dilemma, competing in many markets with its own customers, which can make it less neutral and sometimes less welcome.

By contrast, partnerships like TSMC with SK hynix and Micron, and the standards they support and help define, are more likely to offer the industry clearer and more convincing reasons to adopt their approaches.

 

[Xebec]

The zHBM looks like exactly what d-Matrix did here: https://ramyadhadidi.github.io/files/dMatrix-Raptor-ISCA.pdf. They had to do a DRAM re-design, banks and all. The real mystery is who made this DRAM and stacked it on their logic die from TSMC.

Advanced Package Solutions - Alchip

www.alchip.com

d-Matrix and Alchip Announces Collaboration on World's First 3D DRAM Solution to Supercharge AI Inference-Alchip

www.alchip.com

This firm was involved with the d-matrix / Raptor team and appears to be involved in some of the packaging work here.

 

[Fred Chen]

Advanced Package Solutions - Alchip

www.alchip.com

d-Matrix and Alchip Announces Collaboration on World's First 3D DRAM Solution to Supercharge AI Inference-Alchip

www.alchip.com

This firm was involved with the d-matrix / Raptor team and appears to be involved in some of the packaging work here.

Ah I see, thanks for the information!

Unfortunately, they use the "3D DRAM" terminology which could be confusing and is inaccurate. It's more appropriate to say something like "DRAM-on-logic" for example.

 

[blueone]

Samsung is an IDM that also serves external foundry customers, and it naturally wants to play a bigger role in defining standards and technology approaches that support its logic design, foundry, memory, and device businesses. But Samsung also faces a classic IDM dilemma, competing in many markets with its own customers, which can make it less neutral and sometimes less welcome.

Intel led the definition of multiple important industry specifications while being an IDM, including PCI Express and NVMe.

By contrast, partnerships like TSMC with SK hynix and Micron, and the standards they support and help define, are more likely to offer the industry clearer and more convincing reasons to adopt their approaches.

Micron and SK Hynix are both IDMs in SSDs.

 

[siliconbruh999]

With the advancement of AI and advanced packaging, the power to define standards and requirements has increasingly shifted to the foundries.

Samsung is an IDM that also serves external foundry customers, and it naturally wants to play a bigger role in defining standards and technology approaches that support its logic design, foundry, memory, and device businesses. But Samsung also faces a classic IDM dilemma, competing in many markets with its own customers, which can make it less neutral and sometimes less welcome.

This is just LOL. Like Blueone said Intel has many industry specifications that's a moot point.

By contrast, partnerships like TSMC with SK hynix and Micron, and the standards they support and help define, are more likely to offer the industry clearer and more convincing reasons to adopt their approaches.

Yeah no this is totally wrong. Adopting a memory standard is eased by if it's JEDEC not proprietary.

 

[linkpolo]

View attachment 5060

Samsung Electronics has set out an ambitious 3D-memory roadmap designed to strengthen its position in the fast-growing market for artificial-intelligence infrastructure. Unveiled at the Future of Memory and Storage 2026 conference, the strategy centers on bringing memory physically closer to AI accelerators, increasing bandwidth while cutting energy use and data-transfer delays.

Its headline concept, zHBM, places high-bandwidth memory directly above an accelerator instead of beside it. Samsung says a future zHBM interface could deliver roughly eight times the performance of HBM5, more than ten times its memory density, threefold better energy efficiency, and over 50% lower thermal resistance. The design could also incorporate customer-specific intellectual property between the memory and processor, supporting more specialized AI systems.

Samsung also introduced zNAND-O, a four- or eight-layer NAND architecture aimed at edge AI, where low latency and efficient local processing are critical. More immediately, its V10 Bonding V-NAND prototype uses wafer bonding and exceeds 400 layers. The company claims it raises density by about 58% over V9 while improving read, write, and input/output performance.

The roadmap extends across HBM4E, HBM5, processing-in-memory LPDDR5X, and enterprise storage, reflecting Samsung’s effort to offer an integrated stack spanning memory, foundry, and advanced packaging. For AI technology leaders, the significance is architectural: model performance increasingly depends not only on faster processors, but on reducing the cost, heat, and latency of moving data. Samsung’s concepts remain forward-looking, so customer qualification, manufacturing yield, thermals, pricing, and delivery schedules will determine whether the roadmap becomes a competitive advantage at scale.

https://www.bloomberg.com/news/articles/2026-08-04/samsung-reveals-new-3d-memory-roadmap-in-bid-for-ai-tech-lead

space waves

The shift toward bringing memory closer to AI accelerators is becoming just as important as pushing raw compute performance. zHBM looks especially interesting if Samsung can turn those projected bandwidth, efficiency, and thermal gains into something manufacturable at scale.

 

[Xebec]

Ah I see, thanks for the information!

Unfortunately, they use the "3D DRAM" terminology which could be confusing and is inaccurate. It's more appropriate to say something like "DRAM-on-logic" for example.

Agreed, I was going to ask if there was a hidden paper with actually stacked 3D DRAM shown

 

[Xebec]

This is just LOL. Like Blueone said Intel has many industry specifications that's a moot point.

Yeah no this is totally wrong. Adopting a memory standard is eased by if it's JEDEC not proprietary.

Are you still using your Rambus DIMMs?

 

[Paul2]

I wonder, if them going for stacked DRAM is an indication that their decades long mono-3D DRAM is not coming soon, or they are confident that they can squeeze stacked DRAM, and sell enough of it to recoup the investment in the limited time before mono-3D will become a norm?

 

[hist78]

This is just LOL. Like Blueone said Intel has many industry specifications that's a moot point.

Yeah no this is totally wrong. Adopting a memory standard is eased by if it's JEDEC not proprietary.

My original post was talking about more than just memory standards or specifications. But if we focus strictly on memory standard setting, Intel has had a very unhappy history. Two major failed attempts were RDRAM (Rambus DRAM) and 3D XPoint/Optane. They failed for multiple reasons, but one of them was that other industry players did not want to be locked into something Intel controlled or heavily influenced, especially when it conflicted with their own interests.

The first sentence of @Daniel Nenni’s original post reads:

“Samsung Electronics has set out an ambitious 3D‑memory roadmap designed to strengthen its position in the fast‑growing market for artificial‑intelligence infrastructure.”

Do you think SK Hynix or Micron will be eager to endorse Samsung’s roadmap to strengthen Samsung’s position?

Will Apple, AMD, Nvidia, Qualcomm, Microsoft, Google, or even Intel show enthusiasm for following Samsung’s proposal? I think that’s questionable.

A dedicated foundry service company like TSMC poses no threat to memory makers, fabless design houses, IP developers, or many others. @Daniel Nenni posted an article last year that included the TSMC Open Innovation Platform (OIP) diagram.

In the TSMC OIP 3DFabric section, SK Hynix, Micron, and Samsung Memory all show up. I doubt Samsung could produce a similar diagram with SK Hynix and Micron listed as supporters.

Source: https://semiwiki.com/semiconductor-...icient-ai-innovations-in-logic-and-packaging/

 

[Fred Chen]

I wonder, if them going for stacked DRAM is an indication that their decades long mono-3D DRAM is not coming soon, or they are confident that they can squeeze stacked DRAM, and sell enough of it to recoup the investment in the limited time before mono-3D will become a norm?

The stacking of DRAM dies with TSVs has a different purpose from the stacking of cell layers on one die. They should evolve independently.

The TSVs are for bandwidth, and the main innovation with d-Matrix and other similar endeavors is that the DRAM dies are stacked in the same stack as the logic die, rather than beside it on the interposer.

Having many cell layers on one die is to address density, when lateral scaling poses electrical issues such as leakage and easier disturb of adjacent word lines (RowHammer/RowPress).

 

[Xebec]

“Samsung Electronics has set out an ambitious 3D‑memory roadmap designed to strengthen its position in the fast‑growing market for artificial‑intelligence infrastructure.”

Do you think SK Hynix or Micron will be eager to endorse Samsung’s roadmap to strengthen Samsung’s position

JEDEC adoption may not apply or matter here. All Samsung needs to do is make sure the end product confirms to JEDEC electrical and physical standards. As long as the 3D DRAM is packaged/interfaced properly it can still sit on a JEDEC standard memory stick.

(The dies inside memory chips are certainly all different sizes, while the final package is what has to work with a ddr dimm).

 

[siliconbruh999]

Are you still using your Rambus DIMMs?

I have switched to MRDIMMs or Mister DIMM from Intel that's now jedec standard

 

[siliconbruh999]

My original post was talking about more than just memory standards or specifications. But if we focus strictly on memory standard setting, Intel has had a very unhappy history. Two major failed attempts were RDRAM (Rambus DRAM) and 3D XPoint/Optane. They failed for multiple reasons, but one of them was that other industry players did not want to be locked into something Intel controlled or heavily influenced, especially when it conflicted with their own interests.

RDRAM was failed yes but Optane failure was not due to technology and nor it was a JEDEC Standard it's entirely due to cost.

The first sentence of @Daniel Nenni’s original post reads:

“Samsung Electronics has set out an ambitious 3D‑memory roadmap designed to strengthen its position in the fast‑growing market for artificial‑intelligence infrastructure.”

Do you think SK Hynix or Micron will be eager to endorse Samsung’s roadmap to strengthen Samsung’s position?

Will Apple, AMD, Nvidia, Qualcomm, Microsoft, Google, or even Intel show enthusiasm for following Samsung’s proposal? I think that’s questionable.

A dedicated foundry service company like TSMC poses no threat to memory makers, fabless design houses, IP developers, or many others. @Daniel Nenni posted an article last year that included the TSMC Open Innovation Platform (OIP) diagram.

In the TSMC OIP 3DFabric section, SK Hynix, Micron, and Samsung Memory all show up. I doubt Samsung could produce a similar diagram with SK Hynix and Micron listed as supporters.



View attachment 5063

View attachment 5064


Source: https://semiwiki.com/semiconductor-...icient-ai-innovations-in-logic-and-packaging/

Many of those partners are common among Intel / TSMC

 

[blueone]

My original post was talking about more than just memory standards or specifications. But if we focus strictly on memory standard setting, Intel has had a very unhappy history. Two major failed attempts were RDRAM (Rambus DRAM) and 3D XPoint/Optane. They failed for multiple reasons, but one of them was that other industry players did not want to be locked into something Intel controlled or heavily influenced, especially when it conflicted with their own interests.

Neither assertion here is correct.

Optane was never intended to be "an industry standard". It was simply a new memory technology developed jointly by Intel and Micron, and Intel intended to keep their system implementation proprietary. (I don't know what Micron's product plans for Optane were.) Simply put, Optane was intended to be a main memory extension layer in clients and servers. Intel's financial goals were to reduce the share of wallet of DRAM vendors in client and server systems, and increase Intel's share of wallet by being a memory provider. The system implementations were complex, as Optane required sophisticated DRAM caches for memory system use. (The write endurance for Optane, while better than flash, was far lower than DRAM.) Optane also had an expensive 3D scaling strategy, called "decks", which was challenging for Micron.

Optane also had an architecture difference with DRAM, in that Optane writes were persistent even after power-down. This made Optane irresistible to some companies like Oracle and Vast Data which needed persistent low-latency data and transaction logging, but their use models and markets were not enough to save Optane.

What killed Optane was a combination of factors, not the least of which was a poor reception of Intel's proprietary memory system design strategy by server OEMs. Only vertically integrated vendors like Oracle and various appliance producers were interested.

As for RDRAM, it died because the generational evolution of DDR memory eliminated most of the performance advantages of RDRAM at lower cost.