Open source AMS/RF/digital simulation (don't pay more)

[simguru]

Thanks to Claude I got to build the simulator I wanted to build ~ 15 years ago.

SystemVerilog to VHDL Translator for Federated Simulation

sv2ghdl translates SystemVerilog RTL into VHDL for use with GHDL and NVC simulators. The generated VHDL leverages simulator extensions that go beyond what SystemVerilog offers, including multi-UDN wires, bidirectional components, and improved unknown-state handling.

It's a mash of iverilog, nvc, yosys and xyce -

sv2ghdl/README.md at main · kev-cam/sv2ghdl

Translator for SystemVerilog DUT code to gHDL compatible VHDL code. - kev-cam/sv2ghdl

github.com

The goal is to replace all old crufty commercial simulators with something that works properly and performs better, current numbers are for the free analog simulators -

sv2ghdl/bfit/benchmarks/perf.md at main · kev-cam/sv2ghdl

Translator for SystemVerilog DUT code to gHDL compatible VHDL code. - kev-cam/sv2ghdl

github.com

The money-making proposition (for me) is in this specialist modeling, so I'm letting people use the base simulator for free, this tool is the only way to catch CDC bugs with functional simulation -

GitHub - kev-cam/stat-sim

Contribute to kev-cam/stat-sim development by creating an account on GitHub.

github.com

Here's a freebie PLL generator -

GitHub - kev-cam/kestrel: PLL generator based on TCI's expired patents.

PLL generator based on TCI's expired patents. Contribute to kev-cam/kestrel development by creating an account on GitHub.

github.com

YMMV, get in touch if you want it tuned for something specific.

 

[coldsolder215]

Nice, I really hope AI enables a golden age of open source, after decades of open source being used to underwrite closed source. I've been using xyce with Claude and have been very impressed with what it can handle. Substituting a GUI for a natural language interface is not a terrible tradeoff, particularly for analog design. It dives in to debug convergence issues and generate initial conditions. I even had it characterizing black box LTspice behaviorals and porting them to xyce. Fun times.

 

[simguru]

I have drop-in replacement for LTspice using WSL - https://github.com/kev-cam/ltz - and Qspice. The benchmark page above shows ngspice and Xyce beating them using Verilog-A substitutions for common circuit patterns.

NB: I have my own version of Xyce with a Python/GiNaC based Verilog-A compiler. See if you can get your black-box characterizer to throw out Verilog-AMS (that was on my to-do list).

Claude is grinding through making nvc match Verilator at the moment, but VCS is an easier target if anyone wants it replaced by something faster.