Japan’s Rapidus Takes on TSMC With Aggressive 2nm Pricing

[Daniel Nenni]

The race for advanced nodes among foundries is shifting beyond a battle over technology timelines, with emerging challengers also competing on pricing. According to Nikkei, Rapidus, which is targeting 2nm mass production in 2027, plans to price its foundry services at levels comparable to or lower than those of industry leader TSMC as it seeks to gain a foothold in the market.

Nikkei, citing Rapidus CEO Atsuyoshi Koike, reports that the company aims to “at least match, or slightly undercut” TSMC’s pricing for its products. Rapidus is targeting a reference price of ¥3 million to ¥3.5 million per wafer, although the final price could fluctuate depending on factors such as exchange rates, the report adds. At current rates, the range translates to approximately US$18,460 to US$21,540 per wafer.

Meanwhile, Rapidus is accelerating customer engagement efforts, holding discussions with more than 60 companies, the majority of which are overseas customers, according to Nikkei. The company is also looking beyond its initial 2nm ramp-up, targeting 1.4nm production in 2029, with its planned second fab in Chitose, Hokkaido, expected to support future capacity expansion, according to the Yomiuri Shimbun.

2nm Pricing Battle Intensifies Among Foundry Giants​

Rapidus’ aggressive pricing strategy is putting established foundry leaders under renewed scrutiny. According to Business Post, TSMC’s 2nm process and Intel’s 18A (1.8nm-class) node are reportedly priced at around US$30,000 per wafer. If accurate, the pricing would be significantly above Rapidus’ targeted pricing of up to US$21,000 per wafer.

In comparison, Samsung Electronics’ 2nm process is estimated at approximately US$20,000 per wafer, highlighting its more aggressive pricing stance as it seeks to attract advanced-node customers, Business Post notes.

Nonetheless, both foundry giants are said to be raising prices amid surging demand and tight capacity. Industry sources cited by Chosun Biz noted that TSMC has recently informed major customers, including NVIDIA, Apple, and AMD, of plans to raise wafer prices by 5% to 10% for advanced processes such as 3nm and 5nm, as well as the 7nm node widely used for high-performance semiconductor production.

A similar trend is emerging at Samsung’s foundry business as well. According to Chosun Biz, Samsung is raising supply prices for new customers by around 15%, mainly for high-demand advanced nodes such as 4nm and 5nm, as well as selected 8nm nodes used for automotive semiconductors.

However, unlike TSMC’s broader pricing increase strategy, Samsung’s adjustments are viewed as more targeted price normalization focused on specific processes with strong demand, the report suggests.

[News] Japan’s Rapidus Takes on TSMC With Aggressive 2nm Pricing, Reportedly Targeting up to ¥3.5M per Wafer

The race for advanced nodes among foundries is shifting beyond a battle over technology timelines, with emerging challengers also competing on pricing...

www.trendforce.com

 

[MKWVentures]

The race for advanced nodes among foundries is shifting beyond a battle over technology timelines, with emerging challengers also competing on pricing. According to Nikkei, Rapidus, which is targeting 2nm mass production in 2027, plans to price its foundry services at levels comparable to or lower than those of industry leader TSMC as it seeks to gain a foothold in the market.

Nikkei, citing Rapidus CEO Atsuyoshi Koike, reports that the company aims to “at least match, or slightly undercut” TSMC’s pricing for its products. Rapidus is targeting a reference price of ¥3 million to ¥3.5 million per wafer, although the final price could fluctuate depending on factors such as exchange rates, the report adds. At current rates, the range translates to approximately US$18,460 to US$21,540 per wafer.

Meanwhile, Rapidus is accelerating customer engagement efforts, holding discussions with more than 60 companies, the majority of which are overseas customers, according to Nikkei. The company is also looking beyond its initial 2nm ramp-up, targeting 1.4nm production in 2029, with its planned second fab in Chitose, Hokkaido, expected to support future capacity expansion, according to the Yomiuri Shimbun.

2nm Pricing Battle Intensifies Among Foundry Giants​

Rapidus’ aggressive pricing strategy is putting established foundry leaders under renewed scrutiny. According to Business Post, TSMC’s 2nm process and Intel’s 18A (1.8nm-class) node are reportedly priced at around US$30,000 per wafer. If accurate, the pricing would be significantly above Rapidus’ targeted pricing of up to US$21,000 per wafer.

In comparison, Samsung Electronics’ 2nm process is estimated at approximately US$20,000 per wafer, highlighting its more aggressive pricing stance as it seeks to attract advanced-node customers, Business Post notes.

Nonetheless, both foundry giants are said to be raising prices amid surging demand and tight capacity. Industry sources cited by Chosun Biz noted that TSMC has recently informed major customers, including NVIDIA, Apple, and AMD, of plans to raise wafer prices by 5% to 10% for advanced processes such as 3nm and 5nm, as well as the 7nm node widely used for high-performance semiconductor production.

A similar trend is emerging at Samsung’s foundry business as well. According to Chosun Biz, Samsung is raising supply prices for new customers by around 15%, mainly for high-demand advanced nodes such as 4nm and 5nm, as well as selected 8nm nodes used for automotive semiconductors.

However, unlike TSMC’s broader pricing increase strategy, Samsung’s adjustments are viewed as more targeted price normalization focused on specific processes with strong demand, the report suggests.

[News] Japan’s Rapidus Takes on TSMC With Aggressive 2nm Pricing, Reportedly Targeting up to ¥3.5M per Wafer

The race for advanced nodes among foundries is shifting beyond a battle over technology timelines, with emerging challengers also competing on pricing...

www.trendforce.com

Some questions on Rapidus:
1) Their pilot line came up a year ago. But I have not seen cross sections or summary of the process technology..... have other people seen this?

2) If Rapidus is going to have volume in late 2027 as committed, then the chip design must be in progress and a tapeout is needed soon to run checkout. Rapidus has stated that there are no committments yet. Is Rapidus really a 2030 potential volume as opposed to 2027 potential volume?

3) More specifically, Are there customers today planning to work with them and starting designs?

As mentioned in the article, being aggressive on pricing to gain share will cause losses in addition to the losses from ramping up. Jumping into foundry is financially very difficult. We will see if Intel confims this with a "Due to getting customers on 18A and 14A, will will not break even in 2027 as committted multiple times" statement

 

[Daniel Nenni]

I met with Rapidus last year after Hot Chips. They were pitching faster turn around time than TSMC. No mention of pricing.

My suggestion was get a couple of trusted customers, like TSMC has with: Nvidia, Apple, Nvidia, QCOM, etc... co develop and customize the process.

I also wonder about the Japan market and the many investors in Rapidus. Are they not buying wafers? It seems like capacity would be more of an issue than cutting prices to get customers.

 

[Artificer60]

I met with Rapidus last year after Hot Chips. They were pitching faster turn around time than TSMC. No mention of pricing.

Faster turn around time surprises me. That would imply one or all of the following:

A more efficient system to process orders and get wafers started​

A more efficient design flow to move wafers through design and test lot validation to production​

Better tool up time performance​

A shorter process flow (fewer mask layers in particular)​

None of these seem very likely to me given TSMCs decades of experience to perfect these metrics.

I guess the one thing I could see at least earlier on is faster throughput from lower factory loadings. Wafers spend far more time waiting to be processed than they actually spend on the process tools. It is just a natural effect of queuing. The more wafers in the fab relative to the tools you have to run them on, the more time wafers get held up waiting.

As you can see in the image below this response is non-linear and the more heavily you load the fab the longer it takes to run the wafers. The problem is low loadings (expressed in wafer starts per day here) are expensive. And while the time in the fab grows exponential as factory loadings increase you still only get out the volume that you start in a given day. I have no doubt TSMC runs in the sweet spot on this curve, but the only realistic way I can see for Rapidus to have better turn around time than TSMC is to under load their factory and make less money (fewer wafers to sell for equivalent production costs).

 

[Fred Chen]

Faster turn around time surprises me. That would imply one or all of the following:

A more efficient system to process orders and get wafers started​

A more efficient design flow to move wafers through design and test lot validation to production​

Better tool up time performance​

A shorter process flow (fewer mask layers in particular)​

None of these seem very likely to me given TSMCs decades of experience to perfect these metrics.

I guess the one thing I could see at least earlier on is faster throughput from lower factory loadings. Wafers spend far more time waiting to be processed than they actually spend on the process tools. It is just a natural effect of queuing. The more wafers in the fab relative to the tools you have to run them on, the more time wafers get held up waiting.

As you can see in the image below this response is non-linear and the more heavily you load the fab the longer it takes to run the wafers. The problem is low loadings (expressed in wafer starts per day here) are expensive. And while the time in the fab grows exponential as factory loadings increase you still only get out the volume that you start in a given day. I have no doubt TSMC runs in the sweet spot on this curve, but the only realistic way I can see for Rapidus to have better turn around time than TSMC is to under load their factory and make less money (fewer wafers to sell for equivalent production costs).

View attachment 4866

Rapidus had mentioned before that they were doing single-wafer processing rather than batches: https://www.rapidus.inc/en/tech/te0001/. So their customers need to be patient.

 

[Barnsley]

Faster turn around time surprises me. That would imply one or all of the following:

A more efficient system to process orders and get wafers started​

A more efficient design flow to move wafers through design and test lot validation to production​

Better tool up time performance​

A shorter process flow (fewer mask layers in particular)​

None of these seem very likely to me given TSMCs decades of experience to perfect these metrics.

I guess the one thing I could see at least earlier on is faster throughput from lower factory loadings. Wafers spend far more time waiting to be processed than they actually spend on the process tools. It is just a natural effect of queuing. The more wafers in the fab relative to the tools you have to run them on, the more time wafers get held up waiting.

As you can see in the image below this response is non-linear and the more heavily you load the fab the longer it takes to run the wafers. The problem is low loadings (expressed in wafer starts per day here) are expensive. And while the time in the fab grows exponential as factory loadings increase you still only get out the volume that you start in a given day. I have no doubt TSMC runs in the sweet spot on this curve, but the only realistic way I can see for Rapidus to have better turn around time than TSMC is to under load their factory and make less money (fewer wafers to sell for equivalent production costs).

View attachment 4866

How about getting to the wafer stage.

I notice on here , nothing before the foundry appears to matter.

 

[Xebec]

As you can see in the image below this response is non-linear and the more heavily you load the fab the longer it takes to run the wafers. The problem is low loadings (expressed in wafer starts per day here) are expensive. And while the time in the fab grows exponential as factory loadings increase you still only get out the volume that you start in a given day. I have no doubt TSMC runs in the sweet spot on this curve, but the only realistic way I can see for Rapidus to have better turn around time than TSMC is to under load their factory and make less money (fewer wafers to sell for equivalent production costs).

Is it an accurate interpretation of this chart that:

- The higher the throughput, the less you can change the masks (products) - meaning a new customer asking for something, or a chance to an existing SKU will take longer to initially get into the process flow?

 

[Artificer60]

Is it an accurate interpretation of this chart that:

- The higher the throughput, the less you can change the masks (products) - meaning a new customer asking for something, or a chance to an existing SKU will take longer to initially get into the process flow?

I'm not sure about the assumptions baked into this specific image. My assumption is that it is just a basic queuing curve with a 1000 wspd maximum.

Typically, planned maintenance is factored into the capacity number, so if all tools were up and running and never needed maintenance the maximum throughput would be higher. If mask changes and other tool set up requirements are factored in it will just be some sort of fudge factor unless you have long term contracts in place for the products you will run in your factory. That is an advantage that TSMC has in having more demand than capacity. They can decide what a factory will run when it is being designed and do a pretty good job of ensuring they have the capacity to achieve the velocity they want.

The key factor is the factory capacity and how close you are to reaching that capacity. As a general rule as your product mix becomes more diversified a factory's capacity is reduce. So if you add more products you either reduce the expected output of the factory, or you accept the hit to throughput time.

 

[hist78]

Faster turn around time surprises me. That would imply one or all of the following:

A more efficient system to process orders and get wafers started​

A more efficient design flow to move wafers through design and test lot validation to production​

Better tool up time performance​

A shorter process flow (fewer mask layers in particular)​

None of these seem very likely to me given TSMCs decades of experience to perfect these metrics.

I guess the one thing I could see at least earlier on is faster throughput from lower factory loadings. Wafers spend far more time waiting to be processed than they actually spend on the process tools. It is just a natural effect of queuing. The more wafers in the fab relative to the tools you have to run them on, the more time wafers get held up waiting.

As you can see in the image below this response is non-linear and the more heavily you load the fab the longer it takes to run the wafers. The problem is low loadings (expressed in wafer starts per day here) are expensive. And while the time in the fab grows exponential as factory loadings increase you still only get out the volume that you start in a given day. I have no doubt TSMC runs in the sweet spot on this curve, but the only realistic way I can see for Rapidus to have better turn around time than TSMC is to under load their factory and make less money (fewer wafers to sell for equivalent production costs).

View attachment 4866

Traditionally in manufacturing, high volume is associated with lower variance and fewer product types. Conversely, a high number of products and greater variance result in lower volume for each product. It is neither easy nor practical to achieve both high volume and high variance at the corporate or enterprise level. TSMC is a unique exception.


From TSMC 2025 Annual Report, Published in March 2026:

"We deployed 305 distinct process technologies, and manufactured 12,682 products for 534 customers."

 

[hist78]

Traditionally in manufacturing, high volume is associated with lower variance and fewer product types. Conversely, a high number of products and greater variance result in lower volume for each product. It is neither easy nor practical to achieve both high volume and high variance at the corporate or enterprise level. TSMC is a unique exception.


From TSMC 2025 Annual Report, Published in March 2026:

"We deployed 305 distinct process technologies, and manufactured 12,682 products for 534 customers."

To put the TSMC volume into perspective:

Also from TSMC 2025 Annual Report, published in March 2026:

"Total wafer shipments were 15.0 million 12-inch equivalent wafers as compared to 12.9 million 12-inch equivalent wafers in 2024."

That's 15 million 12-inch equivalent wafers for "305 distinct process technologies, and manufactured 12,682 products for 534 customers".

 

[Xebec]

To put the TSMC volume into perspective:

Also from TSMC 2025 Annual Report, published in March 2026:

"Total wafer shipments were 15.0 million 12-inch equivalent wafers as compared to 12.9 million 12-inch equivalent wafers in 2024."

That's 15 million 12-inch equivalent wafers for "305 distinct process technologies, and manufactured 12,682 products for 534 customers".

Stepping back - each one of those chips are the most complex things made on Earth..

 

[Daniel Nenni]

Stepping back - each one of those chips are the most complex things made on Earth..

Absolutely. It will be a true test of IBM technology for High Volume Manufacturing.