Intel Solves 18A Yield Issues, Production Reaches 30,000 Wafers Per Month

[Daniel Nenni]

Intel has reportedly resolved all yield issues it experienced with its 18A node over the past few months. According to the sell-side equity research firm BlueFin Research Partners, Intel has fixed these yield issues, making the high-volume production of its latest node sustainable from both a manufacturing yield and economic standpoint. Readers may recall that late last year, Intel confirmed that 18A yields were improving by about 7% per month over several months. This trend continued into the launch of the first 18A product, codenamed "Panther Lake," up until today, when the yield issues have reportedly been resolved. For a mature node, this usually means defect rates of D0=0.1 or D0=0.2, and it is likely that Intel has now achieved the lower end of that spectrum with the node advancements and months of 18A high-volume production.

Regarding manufacturing capacity, the report notes that Intel's 18A is produced at two sites: Fab 52 in Phoenix, Arizona, and another in Hillsboro, Oregon. These fabs currently produce about 30,000 wafers per month with the 18A printing. This capacity is currently sufficient for Intel's internal production, such as the "Panther Lake" processors, but additional capacity will be needed for other internal products.

For the remaining nodes, Intel has started 18A-P risk production at the D1X site in Oregon, with plans to transfer the 18A-P node to Fab 62 for long-term high-volume manufacturing. Early 14A results from sample production show a promising path to success, and Intel plans to use the D1X fab for initial high-volume production, with Ohio sites for the second 14A high-volume manufacturing. For external customers, Intel's offerings will focus mainly on 18A-P, 18A-PT, and the upcoming 14A node, which will begin risk production in 2028, with high-volume production slated for 2029.

Intel Solves 18A Yield Issues, Production Reaches 30,000 Wafers Per Month

Intel has reportedly resolved all yield issues it experienced with its 18A node over the past few months. According to the sell-side equity research firm BlueFin Research Partners, Intel has fixed these yield issues, making the high-volume production of its latest node sustainable from both a...

www.techpowerup.com

 

[Daniel Nenni]

Actually it is higher than that which is the problem with yield. By the time you publish a number it is obsolete. GO INTEL!

The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes

Key takeaways▼

• Intel 18A success hinges on yield improvement to restore confidence and advance foundry ambitions.
• Advanced nodes increase complexity; traditional SPC is insufficient as RibbonFET and PowerVia generate massive integration data.
• PDF Solutions Exensio platform unifies equipment, metrology, inspection, test, and design data to accelerate root cause analysis.
• Intel and PDF collaborate on data infrastructure, AI, and design integration to scale 18A and enable 14A readiness.
• Data driven yield management and AI analytics will be essential for rapid yield ramps and foundry credibility at 14A and beyond.

The Yield Partnership: Intel and PDF Solutions Tackle Advanced Nodes - Semiwiki

One of the most difficult things to do in life is ask for help. This is inherently a big problem in the semiconductor industry dating back to the IDM days where silos of secrecy were established. As a result Intel has struggled with yield since the 14nm FinFET process nodes. On the outside PDF...

semiwiki.com

 

[MKWVentures]

I dont know that I would use the term "solves yield". they have improved yields significantly

wafer die (probe) yields are more reasonable now. Per LBT, YIelds were terrible when Intel claimed 18A was manufacturing ready and running in risk production. But really not that terrible considering they were 9 months from PRQ.
Intel is ramping 18A quickly in Q2/Q3.
Fab 52 is not at planned capacity yet. Note: the fab can running "full" and not be at planned capacity due to tool output issues.
The key is not really die yields at this point, it is wafer cost. Intel needs to get to planned capacity, output per tool, and wafer cost to reduce losses.

Intels foundry issue is not whether they are capable of 18A or 14A. Its is whether they can make money manufacturing.

Great question for Intel at the next earnings: "How do the margins compare for TSMC Arrow lake, Intel 4/3 meteor lake, 18A panther lake, and Intel7 raptor lake". are 18A product margins higher than TSMC products and Intel 7 Products?"

I look forward to some nice profitability insights in Q2 and Q3 earnings calls and updates on fab roadmap timing

 

[Daniel Nenni]

Great question for Intel at the next earnings: "How do the margins compare for TSMC Arrow lake, Intel 4/3 meteor lake, 18A panther lake, and Intel7 raptor lake". are 18A product margins higher than TSMC products and Intel 7 Products?"

Absolutely! I will pass the word.

Any other questions that should be asked? Anyone? I will make a list.

 

[siliconbruh999]

Absolutely! I will pass the word.

Any other questions that should be asked? Anyone? I will make a list.

I want to know what are the plans for external vs internal how do they plan to balance it out like are they looking at more external wafers going forward or more Internal going forward also how are they going to compete with gap in their DC Roadmap after the 8CH DMR Platform was killed.

 

[Geddagod]

Absolutely! I will pass the word.

Any other questions that should be asked? Anyone? I will make a list.

Similar to what @siliconbruh999 asked, but is NVL planned to use a higher percent of internal wafers than PTL? I believe in the past they said they would use more internal wafers for NVL than PTL, but not sure if that was in terms of just total wafer count, or percent (which they have claimed is 70% internal and 30% external for PTL).

 

[MKWVentures]

Similar to what @siliconbruh999 asked, but is NVL planned to use a higher percent of internal wafers than PTL? I believe in the past they said they would use more internal wafers for NVL than PTL, but not sure if that was in terms of just total wafer count, or percent (which they have claimed is 70% internal and 30% external for PTL).

I think NVL is already committed to 90% external. CPU+Graphics+IO). It replaces Arrow lake which is 100% external. @siliconbruh999 might know more. PTL has this wierd items where the small GPU is Intel and the large one is
TSMC .... I think it is mostly large GPU on sales.

 

[Geddagod]

I think NVL is already committed to 90% external. CPU+Graphics+IO). It replaces Arrow lake which is 100% external. @siliconbruh999 might know more. PTL has this wierd items where the small GPU is Intel and the large one is
TSMC .... I think it is mostly large GPU on sales.

Some analysts are holding out hope that the rumors of the 4+8 compute tile (if not the 8+16 tile) being external are false.

 

[siliconbruh999]

I think NVL is already committed to 90% external. CPU+Graphics+IO). It replaces Arrow lake which is 100% external. @siliconbruh999 might know more. PTL has this wierd items where the small GPU is Intel and the large one is
TSMC .... I think it is mostly large GPU on sales.

Well NVL is reverse of ARL in a way that SoC/IO/iGPU Tile is Intel while the compute is TSMC N2P(8+16/8+16 bLLC/4+8) and (4+0) Compute die is Intel also the bigger iGPU is N2P(12Xe3P) as well rest are 18A iGPU Tiles(2/4 Xe3).

 

[OneEng]

The key is not really die yields at this point, it is wafer cost. Intel needs to get to planned capacity, output per tool, and wafer cost to reduce losses.

Hey Mark, That was exactly what I was about to chime in on. This will determine if Intel's big bet pays off or not. I am also wondering how long until we see anything from those God Awful expensive High NA machines. Another big bet, that if it works out could put Intel in a very profitable position.

 

[OneEng]

Well NVL is reverse of ARL in a way that SoC/IO/iGPU Tile is Intel while the compute is TSMC N2P(8+16/8+16 bLLC/4+8) and (4+0) Compute die is Intel also the bigger iGPU is N2P(12Xe3P) as well rest are 18A iGPU Tiles(2/4 Xe3).

I actually think this will end up being a good thing for NVL. My one big concern for BSPDN was hot spots leading ultimately to limiting fmax. This isn't as big a deal in DC and laptop where higher clocks aren't usually demanded, but in desktop?

While I pretty much don't believe the rumors of AMD's Zen 6 reaching 7Ghz (and even if they could, I doubt they would unless forced to do so by NVL), BUT I do believe that N2 is going to be a process that clocks higher than 18A. I think this will be NVL's saving grace.... but I could be wrong.

 

[sit]

Even if Intel has demand to drive adding capacity they’ll operate at a huge financial disadvantage to TSMC due to scale. Splitting capacity between 2 sites means they’ll never achieve true operational efficiency.

What once 30 years ago was a savvy move to provide customers supply chain reliability, is now a millstone when cost optimization requires 1M wafers per year scale.

 

[MKWVentures]

Well NVL is reverse of ARL in a way that SoC/IO/iGPU Tile is Intel while the compute is TSMC N2P(8+16/8+16 bLLC/4+8) and (4+0) Compute die is Intel also the bigger iGPU is N2P(12Xe3P) as well rest are 18A iGPU Tiles(2/4 Xe3).

I knew you would have the info! thx

 

[IanD]

Process/CPU "clock speed" (e.g. "7GHz") is pretty much meaningless unless you also specify library size/density and voltage and power -- you can always push speed up at the cost of density/power using taller libraries, and push speed up at the cost of power by raising voltage, and increase clock speed and power with more pipelining (fewer gates between latches), the question is how much lower density and higher power (and possibly latency) can you accept as a result -- and also how much power density per mm2, which is what causes hot-spots.

Intel's "we'll soon be clocking at 10GHz" from NetBurst days soon shows you where this goes wrong -- and we have CMOS gates clocking at >20GHz in N2, but you certainly wouldn't want to use them to build a CPU... ;-)

 

[siliconbruh999]

Process/CPU "clock speed" (e.g. "7GHz") is pretty much meaningless unless you also specify library size/density and voltage and power -- you can always push speed up at the cost of density/power using taller libraries, and push speed up at the cost of power by raising voltage, and increase clock speed and power with more pipelining (fewer gates between latches), the question is how much lower density and higher power (and possibly latency) can you accept as a result -- and also how much power density per mm2, which is what causes hot-spots.

Intel's "we'll soon be clocking at 10GHz" from NetBurst days soon shows you where this goes wrong -- and we have CMOS gates clocking at >20GHz in N2, but you certainly wouldn't want to use them to build a CPU... ;-)

still sad we didn't get a Tejas 10Ghz

 

[IanD]

still sad we didn't get a Tejas 10Ghz

Have you ever had a BGA in a socket get hot enough to melt the solder balls onto the socket pogo pins? I have... ;-)

 

[OneEng]

Process/CPU "clock speed" (e.g. "7GHz") is pretty much meaningless unless you also specify library size/density and voltage and power -- you can always push speed up at the cost of density/power using taller libraries, and push speed up at the cost of power by raising voltage, and increase clock speed and power with more pipelining (fewer gates between latches), the question is how much lower density and higher power (and possibly latency) can you accept as a result -- and also how much power density per mm2, which is what causes hot-spots.

Intel's "we'll soon be clocking at 10GHz" from NetBurst days soon shows you where this goes wrong -- and we have CMOS gates clocking at >20GHz in N2, but you certainly wouldn't want to use them to build a CPU... ;-)

LMAO. Yep, I remember that well.

But that is really the point, right? NetBurst couldn't clock to 10Ghz because Intel started running into thermal density limit issues.... not because the transistor geometry was physically incapable of switching that quickly .... right? I always wondered how Intel missed something so obvious?

I am guessing that with GAA, we have managed to drastically lower the non-ideal model current leakage? Given a little more thermal headroom, and I am assuming better drive current capabilities, I would expect FMAX to go up over FinFET .... although I suspect that thermal limitations are still going to prevent Intel from producing a 10Ghz "Tejas" .

 

[OneEng]

Even if Intel has demand to drive adding capacity they’ll operate at a huge financial disadvantage to TSMC due to scale. Splitting capacity between 2 sites means they’ll never achieve true operational efficiency.

What once 30 years ago was a savvy move to provide customers supply chain reliability, is now a millstone when cost optimization requires 1M wafers per year scale.

... and THAT is the fundamental dilemma I see Intel has.

Without a continuous funnel of money to help them overcome their inherent volume disadvantage, they can't justify the continuous (and gargantuan) capital expenditure to create on-going node advances.

 

[swka]

LMAO. Yep, I remember that well.

But that is really the point, right? NetBurst couldn't clock to 10Ghz because Intel started running into thermal density limit issues.... not because the transistor geometry was physically incapable of switching that quickly .... right? I always wondered how Intel missed something so obvious?

I am guessing that with GAA, we have managed to drastically lower the non-ideal model current leakage? Given a little more thermal headroom, and I am assuming better drive current capabilities, I would expect FMAX to go up over FinFET .... although I suspect that thermal limitations are still going to prevent Intel from producing a 10Ghz "Tejas" .

the "relief" of less leakage started in finfet already before GAA. The 3D type of transistor structure, however, does create more challenge to dissipate heat. I recall the current carrying capability of each transistors is going down as nodes goes down, due to EM, SHE, ...

 

[benb]

... and THAT is the fundamental dilemma I see Intel has.

Without a continuous funnel of money to help them overcome their inherent volume disadvantage, they can't justify the continuous (and gargantuan) capital expenditure to create on-going node advances.

TSMC has 10 fabs that could receive 2nm where Intel has 2. Of those 10, not every one is exactly matched, there is a range of tool age and the cycle of upgrading equipment is a distribution. Intel insists on matching, has no distribution, the upgrade cycle is synchronized between those 2 sites.

I say “could receive”. It’s so powerful to win business when you can say “could”; when you can accommodate something in 6 months rather than after.a 3 year synchronization has occurred. It’s a pit stop rather than an overhaul. It’s why TSMC keeps winning and winning and Intel can’t compete, fundamentally.