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Intel may expand 2 nm chip outsourcing to TSMC

Daniel Nenni

Founder
Staff member
Not enough of its own? Intel's new chips expand their use of TSMC's 2nm process technology. Razor Lake is reportedly further adopting TSMC's N2X process.

Intel may expand 2 nm chip outsourcing to TSMC.jpg


Intel's Razor Lake is reportedly using TSMC's 2nm N2X process, which will directly benefit TSMC, and companies like Chung Sha and Song Sheng will also see a new wave of business opportunities. (Photo/Reuters)
  • The battle for advanced manufacturing processes in PC processors is heating up again. Recent market news indicates that Intel's next-generation Nova Lake desktop processors will prioritize the adoption of the bLLC large final-level cache, while laptop versions may be delayed until the subsequent Razor Lake-HX generation. More notably, Razor Lake is rumored to utilize TSMC's high-performance 2nm N2X process. If mass production is ultimately achieved, it signifies that Intel's collaboration with TSMC on advanced processes could extend to a wider range of 2nm products. Besides TSMC directly benefiting, companies like Chung-Sha and Song Sheng are expected to see a new wave of business opportunities.
bLLC stands for Big Last-Level Cache. By increasing the capacity of the processor's last-level cache, it reduces the latency of accessing system memory. Chip industry analysts believe that Intel's strategy is directly targeting AMD's 3D V-Cache technology. Industry analysts also believe that although Intel continues to push forward with its own 18A process technology, facing challenges in high-end CPU launch schedules, performance, and production capacity, outsourcing some computing chips to TSMC can reduce the risks associated with relying on a single process technology.

Supply chain sources indicate that Nova Lake, slated for release early next year, will utilize a combination of different process technologies, including Intel's 18A and TSMC's N2P. Razor Lake, on the other hand, may further incorporate N2X. N2X represents a high-performance extension of TSMC's N2 platform, targeting high-frequency CPUs, AI, and HPC applications. It shifts transistor technology from FinFET to nanosheets, increasing the precision required for thin-film deposition, etching, cleaning, and CMP planarization.

As manufacturing processes shrink to 2 nanometers, the requirements for wafer surface flatness and defect control increase, leading to a simultaneous increase in the number of CMP polishing operations and the value of high-end consumables. Among them, Somson is one of the few Taiwanese manufacturers with independent mass production capabilities for CMP polishing pads. Somson's consolidated semiconductor revenue increased by 25% year-on-year in the first half of the year, accounting for 66% of total revenue. Currently, demand for products such as Hard Pads and advanced packaging is strong, and the new Soft Pad production line is expected to begin trial production in the third quarter and gradually enter mass production in the fourth quarter. The company frankly stated that its existing capacity is insufficient and is expanding production through four shifts and two rotations, as well as new plants in Hefei and Central Taiwan Science Park, to meet the demand for advanced processes.

In advanced packaging, Somchip already has two products in mass production for key customers, used in CoWoS and SoIC processes respectively, and demand is increasing rapidly recently. Somchip observes that it is no longer just a single leading manufacturer investing in AI chips and advanced packaging; other international customers are also adopting similar processes. Somchip is leveraging its existing customer track record to expand into overseas markets and broaden its revenue curve in advanced packaging.

Chung-Shock Technology (CSST) has mastered two key products: CMP diamond discs and reclaimed wafers. Diamond discs are used to finish the surface of polishing pads. The more advanced the process node, the higher the requirements for diamond particle uniformity, lifespan, and defect control. CSST's second-quarter revenue was NT$2.49 billion, a year-on-year increase of 17.9%, with a gross margin rising to 40.1% and EPS reaching NT$3.49. Among them, shipments of 2nm and 1.6nm related diamond discs increased rapidly, and the company continued to expand its monthly production capacity, becoming a direct beneficiary of TSMC's advanced process ramp-up.

 
CMP materials is a huge part of the 2nm push in Taiwan and elsewhere. Besides new diamond discs and pads described in this article, there are new slurries, new polish heads, and multiple sensors embedded in the platen, facing the wafer, used to sense the wafer surface to stop polishing at the desired endpoint. There is no part of the fab as dynamic with new materials as CMP is.
 
The plan to increase outsourcing was decided a year ago not new. And they only moved couple of more tiles to TSMC. RZL only has 2 New tiles in the entire product family everything else is reused from Nova Lake.
 
Was this what Pat's "emergency visits" to TSMC were about a few years ago? I remember some publicity, and I assume those visits were too late for N3 capacity (other than long term contracts maybe).
 
The die size is smaller on N2P vs 18AP
"Yes, but" -- BSPD can allow for die size reductions, maybe closing the gap (moderately?) between the two processes.

"Samsung's 2024 Korea Economic Daily remarks, citing foundry PDK VP Lee Sungjae, put a 17% chip-size reduction, 8% performance, and 15% power on BSPDN versus a traditional front-side PDN"

(i.e. 17% chip size reduction on a like-for-like node with and without BSPD)
 
"Yes, but" -- BSPD can allow for die size reductions, maybe closing the gap (moderately?) between the two processes.

"Samsung's 2024 Korea Economic Daily remarks, citing foundry PDK VP Lee Sungjae, put a 17% chip-size reduction, 8% performance, and 15% power on BSPDN versus a traditional front-side PDN"

(i.e. 17% chip size reduction on a like-for-like node with and without BSPD)
Well that's not true for Intel/TSMC cause Intel/TSMC Paper has shown only 5-10% area improvements .
 
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