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Naga Chandrasekaran who is the EVP, CTO, and GM, Intel Foundry. In a meeting with Keybanc told them:Intel, "Expects 14A performance to be within 5% of TSM's A14".
Intel is not afraid of CoPoS. "Sees sustained leadership in advanced packaging with EMIB-T even with TSM introducing CoPoS".
I must say that the news around 14A PPA is truly extraordinary given 14A yields and ramp are extremely aggressive. Intel is finally sticking its neck out to say how their nodes compare with a % range to TSMC. Note goes on to say that Intel has a server part on 14A in 2028. Coral Rapids might not be on 18A-U if that's the case. Coral could be 14A, but I have capacity concerns (2029 is the big ramp, pointing towards 2029 Ohio volume)
TSMC’s CoPoS, generally described as Chip-on-Panel-on-Substrate, and Intel’s EMIB, or Embedded Multi-die Interconnect Bridge, address the same strategic problem: integrating increasingly large, heterogeneous chiplet systems. However, they attack different physical constraints. CoPoS is an...
Naga Chandrasekaran who is the EVP, CTO, and GM, Intel Foundry. In a meeting with Keybanc told them:Intel, "Expects 14A performance to be within 5% of TSM's A14".
How did he come up with this 5% figure? Why is it not 6.23%, 4%, or 4.56%?
Both Intel 14A and TSMC A14 are still in development, which means no real final product has been manufactured on either node. Without real products to test applications and validate performance, is this 5% figure meaningful?
Or perhaps Naga's statement is based on an Intel test chip that went through early trial runs on both Intel 14A and TSMC A14. If this is the case, he can only say there is a performance difference of up to 5% for an "Intel test chip". He can't generalize that 5% to other companies, whose applications and chips may be very different.
How did he come up with this 5% figure? Why is it not 6.23%, 4%, or 4.56%?
Both Intel 14A and TSMC A14 are still in development, which means no real final product has been manufactured on either node. Without real products to test applications and validate performance, is this 5% figure meaningful?
Or perhaps Naga's statement is based on an Intel test chip that went through early trial runs on both Intel 14A and TSMC A14. If this is the case, he can only say there is a performance difference of up to 5% for an "Intel test chip". He can't generalize that 5% to other companies, whose applications and chips may be very different.
I can assure you a marketing person came up with that number. I actually thought Intel 14A would be a bit faster so this is a disappointment. I can assure you TSMC is better on power and area.
I really don't think this will be an issue though given that TSMC capacity is constrained so the NOT TSMC market is alive and well. In fact, I think it will be bigger than ever, absolutely.
Both Intel 14A and TSMC A14 are still in development, which means no real final product has been manufactured on either node. Without real products to test applications and validate performance, is this 5% figure meaningful?
I can assure you a marketing person came up with that number. I actually thought Intel 14A would be a bit faster so this is a disappointment. I can assure you TSMC is better on power and area.
I really don't think this will be an issue though given that TSMC capacity is constrained so the NOT TSMC market is alive and well. In fact, I think it will be bigger than ever, absolutely.
Naga also stated that 18AP PPA is between N3 to N2P, so it’s actual PPA may be a little bit inferior to N2.
And from N2 to A14, it has 30% power reduction or 15% performance gain, 20% chip density improve. So even 14A has 5% lose to A14 in each items (5% performance + 5% density +5% power), it is truely shrink the gap from 18A to N2.
Ps. If 18AP is close to N2, then we can deduce 18A is only reach N3P class.
I am starting to get some feedback from customers and potential customers of TSMC and Intel . Looks like Intel is clearly not leading with 18A vs N2, Intel is closer on 14A (which Naga agrees that Intel goal is to get close).
Intel has improved but TSMC is still ahead. @Daniel Nenni, tell me if you hear differently
Close is nothing to sneeze at when you consider where they were. You can mock 5N4Y all you want, but the bottom line is that Intel has closed a 2 node gap in the last 6 years to something within spitting distance. That is a remarkable accomplishment. I think the graph below does a great job of showing just how bad the 10nm debacle was.
I've seen statements from Lip-Bu Tan saying he expects the foundry turn around to take 10 years. Considering where they are 2 years into his tenure I think they will be in serious player in the foundry industry in another 8 years.
Gelsinger had the right vision, but Intel needed Lip-Bu Tan to bring in the financial discipline and a true customer oriented culture to make this work.
I am starting to get some feedback from customers and potential customers of TSMC and Intel . Looks like Intel is clearly not leading with 18A vs N2, Intel is closer on 14A (which Naga agrees that Intel goal is to get close).
Intel has improved but TSMC is still ahead. @Daniel Nenni, tell me if you hear differently
So if mobile chip, which BSPDN benefit is not large, 14A is within A14 5% PPA performance, then we can expect for high performance HPC chip 14A will be more better than A14?
So if mobile chip, which BSPDN benefit is not large, 14A is within A14 5% PPA performance, then we can expect for high performance HPC chip 14A will be more better than A14?
I am just providing feedback that I got. and reminder that Intel is both a customer of TSMC on N2 and a competitor so they have a solid perspective..... which Naga conveyed publicly
from what I hear, 14A is not expected to be better than A14 for any product on power performance or density. it is expected to be close..... I assume they get this from PDKs and test chip data.
I know BSPD is not useful for mobile. Given the cost and complexity added, it is cost effective for HPC? what about Laptop processors?
How did he come up with this 5% figure? Why is it not 6.23%, 4%, or 4.56%?
Both Intel 14A and TSMC A14 are still in development, which means no real final product has been manufactured on either node. Without real products to test applications and validate performance, is this 5% figure meaningful?
Or perhaps Naga's statement is based on an Intel test chip that went through early trial runs on both Intel 14A and TSMC A14. If this is the case, he can only say there is a performance difference of up to 5% for an "Intel test chip". He can't generalize that 5% to other companies, whose applications and chips may be very different.
I am just providing feedback that I got. and reminder that Intel is both a customer of TSMC on N2 and a competitor so they have a solid perspective..... which Naga conveyed publicly
If you ever wanted proof that this is not the old Intel, I think this is it. Can you imagine anyone under Gelsinger publicly admitting that their next node isn't going to be the best thing since sliced bread. Having a senior exec admit their next process is only going to be close is a breath of fresh air. And that honesty is needed if they are going to win external customers.
Well something other to Note in the summary not it's the base 18A not It's variants there are 18AP/18AU variats. Also something to note Area is missing in the conversation
I am starting to get some feedback from customers and potential customers of TSMC and Intel . Looks like Intel is clearly not leading with 18A vs N2, Intel is closer on 14A (which Naga agrees that Intel goal is to get close).
Intel has improved but TSMC is still ahead. @Daniel Nenni, tell me if you hear differently
I am just providing feedback that I got. and reminder that Intel is both a customer of TSMC on N2 and a competitor so they have a solid perspective..... which Naga conveyed publicly
from what I hear, 14A is not expected to be better than A14 for any product on power performance or density. it is expected to be close..... I assume they get this from PDKs and test chip data.
I know BSPD is not useful for mobile. Given the cost and complexity added, it is cost effective for HPC? what about Laptop processors?
BSPD is not "cost effective", in the sense that -- according to TSMC -- the increase in wafer cost is considerably bigger than the increase in density, so a given design will cost more per chip with BSPD.
Whether the increased density (so you can cram a few more gates on a reticle-sized chip) or higher clock speed is worth the cost premium is a decision only customers can make -- and there's also the BSPD thermal issue so active cooling is essential. So far, very few customers with TSMC (where there's a choice between BSPD and FSPD) have gone with BSPD -- maybe only Nvidia for A16?
With Intel there's no choice now, it's BSPD or nothing -- which may well put a lot of potential customers off, given what is being chosen at TSMC...
