Intel Develops Packaging Technology for Chips Up to 24 Times the Standard Reticle Size
Intel is developing extremely large processor packages that could reach 240mm by 240mm, allowing future AI and high performance computing systems to combine many specialised chiplets within one design.
The company calls the concept Hyper Large Form Factor packaging. Its research targets packages up to 24 times the size of a standard reticle, with longer term plans moving beyond that level through panel based manufacturing.
Intel says its advanced packaging facility in Rio Rancho, New Mexico, has already validated several large EMIB and Foveros designs. An important part of this work involved solving encapsulation problems that become increasingly difficult as packages grow.
The technology is not yet a finished commercial product. However, Intel’s tests suggest that several technical barriers to building much larger chip packages can be addressed through new materials, assembly methods, power delivery and cooling systems.
Intel is developing extremely large processor packages that could reach 240mm by 240mm, allowing future AI and high performance computing systems to combine many specialised chiplets within one design.
The company calls the concept Hyper Large Form Factor packaging. Its research targets packages up to 24 times the size of a standard reticle, with longer term plans moving beyond that level through panel based manufacturing.
Intel says its advanced packaging facility in Rio Rancho, New Mexico, has already validated several large EMIB and Foveros designs. An important part of this work involved solving encapsulation problems that become increasingly difficult as packages grow.
The technology is not yet a finished commercial product. However, Intel’s tests suggest that several technical barriers to building much larger chip packages can be addressed through new materials, assembly methods, power delivery and cooling systems.
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