Semiwiki on LinkedIn Semiwiki on Facebook Semiwiki on Twitter Register / Log in 
Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/intel-accelerates-next-generation-foundry-race-race-with-hi-na-euv-deployment-samsung-electronics-remains-cautious.25546/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/EmailDomainReplace] => 1000010
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2031070
            [XFI] => 1060170
        )

    [wordpress] => /var/www/html
)

Intel Accelerates Next-Generation Foundry 'Race Race' with 'Hi-NA' EUV Deployment... Samsung Electronics Remains Cautious

RFletch

RFletch

New member
Samsung Electronics is taking a more measured approach to next-generation chip manufacturing, choosing to delay broad deployment of High-NA EUV lithography despite already installing two of ASML's latest systems. The move reflects a growing industry reality: advanced manufacturing leadership is no longer defined solely by adopting the newest equipment, but by deploying it when the economics make sense.

The decision comes at a time when High-NA EUV technology is reaching a major commercial milestone. ASML recently confirmed that its High-NA EUV platform has entered high-volume logic manufacturing, with Intel becoming the first semiconductor manufacturer to use the technology in volume production for selected layers of its 18A Panther Lake processors. The company said the technology has now demonstrated production-level readiness, validating years of development.

Samsung, however, appears more focused on restoring the profitability of its foundry business than on accelerating High-NA deployment. According to industry reports, the company believes the substantial depreciation and operating costs associated with High-NA tools outweigh the immediate manufacturing benefits, particularly while foundry utilization remains below optimal levels. As a result, its existing High-NA systems are expected to remain primarily dedicated to research, process optimization, and pilot production rather than large-scale manufacturing.

The cautious strategy also reflects the broader economics of advanced semiconductor manufacturing. Each new process generation demands significantly higher capital investment, and High-NA EUV represents one of the industry's largest equipment expenditures. While the technology offers higher resolution and can reduce multi-patterning complexity, chipmakers must still justify the return on investment through sufficient production volume and customer demand.

Meanwhile, the competitive landscape continues to evolve. TSMC has extended its process technology roadmap through 2029, introducing future nodes including A12, A13, and N2U while adjusting the timing of A16 production to 2027. Rather than rushing into widespread High-NA adoption, TSMC continues balancing technology scaling with manufacturing efficiency and customer requirements, underscoring that different foundries are following distinct paths toward Angstrom-era production.

For Samsung, delaying mass production with High-NA EUV should not be viewed as a retreat from advanced manufacturing. Instead, it represents a strategic effort to improve financial performance before committing to another wave of large-scale capital investment. If foundry demand strengthens and production economics improve, the company is expected to be well positioned to activate its installed High-NA capacity more aggressively.

As AI processors, high-performance computing devices, and next-generation mobile chips continue driving demand for leading-edge silicon, High-NA EUV is widely expected to become an increasingly important manufacturing technology. The current divergence between Intel's early production deployment, Samsung's cost-focused strategy, and TSMC's roadmap-driven approach illustrates that there is no single path to semiconductor leadership. Success will depend not only on owning the most advanced lithography systems, but also on integrating them into a sustainable manufacturing and business strategy.
Some Information are collected from: Trendforce, ASML
Click to expand...
 
1784383751440.png


- Intel First Applies High-NA EUV to Panther Lake:
- "Production Yield Identical to Existing EUV Equipment"
- Samsung Electronics Still Deliberating on Investment… "Foundry Turnaround Comes First"

Intel has become the first company to deploy ASML‘s High-NA EUV in mass production for selected layers of its 18A Panther Lake processors. However, Samsung Electronics has yet to follow despite already installing two High-NA EUV systems. According to Chosun Ilbo, industry observers believe the company’s cautious approach reflects financial considerations rather than technical limitations, as it seeks to avoid further widening foundry losses through additional capital investment.

As highlighted by the report, Samsung installed one High-NA EUV system at its Hwaseong campus last year and added a second in the first half of this year, with total investment estimated at just over KRW 1 trillion. Although Samsung has kept pace with Intel in acquiring High-NA EUV tools, it has yet to officially confirm that the systems have entered mass production, suggesting commercial deployment remains on hold.

Samsung’s foundry business has reportedly remained unprofitable since 2022, although some market observers expect it could return to the black as early as the fourth quarter of this year. For a loss-making business, bringing High-NA EUV tools into full-scale production would substantially raise depreciation and other fixed operating costs. The report adds that, with a turnaround now in sight, Samsung is reluctant to take on additional capital spending.

Chosun Ilbo adds that Samsung’s 2nm yield has reportedly improved to around 55%, approaching the roughly 60% threshold generally regarded as necessary for stable mass production. A semiconductor equipment industry official cited by the report said the company’s yields have reached a level where the new tools could be deployed. Even so, Samsung continues to maintain a conservative capital expenditure strategy until profitability is more firmly supported by orders from major customers.

High-NA EUV Adoption Faces Cost Challenges​

High-NA EUV enables denser circuit patterning in a single exposure, reducing manufacturing complexity by eliminating the need for multi-patterning. As Chosun Ilbo notes, the technology is expected to play an increasingly important role in nodes at 1.4nm and below. Still, cost remains one of the biggest barriers to adoption. Reuters notes that a High-NA EUV system costs around US$400 million—roughly twice as much as a conventional EUV tool—and is also technically challenging to integrate into production.

Tom’s Hardware previously reported that TSMC’s upcoming A13 and A12 process technologies, both targeted for 2029, are not expected to require High-NA EUV lithography. During the earnings call, Chairman and CEO C.C. Wei described High-NA EUV as a promising technology but said its maturity and cost remain important considerations for adoption.

The-High-NA-EUV-divide-2026-819x1024.png

www.chosun.com

인텔, ‘하이NA’ EUV 실전 배치하며 차세대 파운드리 ‘속도전’… 삼성전자는 신중

인텔, 하이NA EUV 실전 배치하며 차세대 파운드리 속도전 삼성전자는 신중 인텔, 팬서레이크에 하이NA EUV 첫 적용 생산 수율은 기존 EUV 장비와 동일 삼성전자는 아직 투자 고심 파운드리 흑자전환이 먼저
www.chosun.com www.chosun.com
 
Samsung remains cautious? :ROFLMAO: Samsung has enough problem with yield without HNA EUV.

Intel is doing the right thing here, blazing trails in a very controlled manner. I have a huge amount of respect for this, this is the Intel I admire. Calling Intel the first foundry to deploy HNA-EUV is a bit of a stretch however.

As I have said before, HNA-EUV does not yield at this time. You can implement a select couple of layers and officially claim HNA-EUV production but it will not be better PPA than a regular EUV process and that is the whole point, right? But someone has to go first and Intel is the perfect company for that.

TSMC has consistently said they are working with ASML on HNA-EUV. TSMC is ASML's largest customer so this tracks. Given that, if TSMC is not using HNA-EUV you really have to wonder why?

“We work with ASML and try to make it more suitable for manufacturing in terms of the cost and in terms of the maturity.”

The simple answer is cost but what does that mean? That means the Return on Investment (ROI) is not acceptable for TSMC customers at this time. That means the design requirements, the resulting PPA, and the yield are not acceptable. It really is as simple as that.
 
"Production Yield Identical to Existing EUV Equipment"

Being able to do even certain layers for 18A means less other equipment and space required to produce the same number of chips. That means that HNA can get away with lower yields and still come out even or ahead on costs; however, it appears even from the article that HNA yields are = to multi-patterned LNA
 
Bdubs82 said:
Being able to do even certain layers for 18A means less other equipment and space required to produce the same number of chips.
Click to expand...
How is this concluded? The High-NA is a much larger piece of equipment. The number of patterning steps is not changed.

Bdubs82 said:
That means that HNA can get away with lower yields and still come out even or ahead on costs
Click to expand...

At the same yield, it is already behind on costs.
 
Fred Chen said:
How is this concluded? The High-NA is a much larger piece of equipment. The number of patterning steps is not changed.



At the same yield, it is already behind on costs.
Click to expand...
Incorrect on both fronts. HNA lowers the # of patterning steps for those layers. this is fundamental.
 
Bdubs82 said:
Fair, but there are still yield advantages to doing HNA at that pitch in terms of yield, energy use, etc.
Click to expand...
Arguably, High-NA has the disadvantage of worse depth of focus. This forces thinner resist, which is harder for yield. Also the field height is different, half the usual 33 mm. So the productivity depends on die or tile height. If it's larger than 16.5 mm, it has to be stitched in two exposures with alignment necessary.
 
You must log in or register to reply here.
Back
Top