Intel 14A pitches Rumour

[Geddagod]

That would land M0 at 22.5nm and if it's 6 Track the cell height would be 135nm and the CGP would likely be 45nm pure guess work on these numbers though.

Thought synopsys already "leaked" N2P cell height and CGP

 

[IanD]

vs N2, or vs N3E?

N2.

 

[siliconbruh999]

N2.

TSMC doesn't list any logic density improvement for N2P

 

[IanD]

Thought synopsys already "leaked" N2P cell height and CGP
View attachment 4842

Those are layout dimensions, which are the same for N2 and N2P -- and you can correctly deduce from this that M1 pitch (same vertical direction as gates) is 48nm. The high density/high speed cells are 5/6 tracks high, so you can deduce from this that the minimum M2 pitch (horizontal interconnect) is 26nm. M0 is used inside cells and for local interconnect, and this is 23nm minimum pitch.

All these dimensions are shrunk by 2% for N2P to get actual physical dimensions on silicon.

 

[IanD]

TSMC doesn't list any logic density improvement for N2P

Yes it does, N2P on-silicon density is 4% better. Layout density is the same since layout is identical to N2, the 2% is a post-layout shrink.