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FROM DIGITIMES:
TSMC is expanding Japan's role in its global network as it prepares to add 3nm production in Kumamoto and deepens local capabilities in advanced packaging, chip design and next-generation image sensors.
TSMC's annual revenue in Japan has risen from about US$150 million when it established its local operation in 1997 to more than US$600 million in 2010 and more than US$4.8 billion in 2025, according to an EE Times Japan interview with TSMC Japan president Makoto Onodera. The company's Japanese operations now support global as well as domestic customers, spanning design, R&D and manufacturing.
Taiwanese authorities have approved TSMC's upgraded plan to manufacture 3nm chips at its second Kumamoto fab. Japan's Ministry of Economy, Trade and Industry described domestic 3nm production as meaningful for the country's economic security, while saying details of additional government support remain under discussion.
The move comes as TSMC expects the global semiconductor market to exceed US$1.5 trillion by 2030, with AI and high-performance computing accounting for 55%. HPC already represented 66% of the company's second-quarter 2026 revenue.
TSMC also raised its 2026 capital budget to US$60-64 billion amid strong demand for leading-edge technologies. About 10%-20% will go to advanced packaging, testing, mask making and other areas.
Sources: EE Times Japan; TSMC; compiled by DIGITIMES Asia
TSMC's 3DIC research center in Tsukuba initially worked with about 40 Japanese companies. That number has grown to roughly 120, creating a larger local network for materials evaluation and joint development of next-generation packaging technologies.
Package dimensions are increasing at the same time. Customer products have already reached the 5.5-reticle scale, while TSMC is now producing 5.5-reticle CoWoS and plans a 14-reticle version for 2028 capable of integrating about 10 large compute dies and 20 HBM stacks. The roadmap extends beyond 14 reticles in 2029, alongside a 40-reticle SoW-X system.
TSMC has projected CoWoS capacity to grow at a compound annual rate of more than 80% from 2022 to 2027. As packages become larger, production based on round wafers could eventually become less efficient, potentially creating a longer-term case for panel-type substrates.
The shift could play to Japanese suppliers' strengths in substrates and packaging materials. TSMC's Tsukuba program has focused on areas including large-area package substrates, high-density packaging materials, thermal management, warpage control and fine-pitch interconnects.
That strategy could deepen through Sony Semiconductor Solutions. The companies signed a non-binding memorandum of understanding in May for a proposed strategic partnership covering the development and manufacturing of next-generation image sensors.
Under the proposal, they intend to establish a joint venture in which Sony would be the majority and controlling shareholder, with development and production lines at Sony's new fab in Koshi City, Kumamoto Prefecture. The JV remains subject to a definitive legally binding agreement and customary closing conditions.
TSMC's overseas expansion was initially driven by long-term customer demand rather than geopolitics, although customers increasingly value geographically diversified supply. Its Japanese design center and Kumamoto manufacturing operations are designed to serve customers globally rather than function as a Japan-only network.
Together, these moves are broadening Japan's place in TSMC's global network across leading-edge manufacturing, advanced packaging R&D, design support and image sensors.
Article edited by Jack Wu
TSMC is expanding Japan's role in its global network as it prepares to add 3nm production in Kumamoto and deepens local capabilities in advanced packaging, chip design and next-generation image sensors.
TSMC's annual revenue in Japan has risen from about US$150 million when it established its local operation in 1997 to more than US$600 million in 2010 and more than US$4.8 billion in 2025, according to an EE Times Japan interview with TSMC Japan president Makoto Onodera. The company's Japanese operations now support global as well as domestic customers, spanning design, R&D and manufacturing.
Japan moves up the value chain
The expansion is now moving into leading-edge manufacturing. On its July 16 earnings call, TSMC(2330.TW) confirmed plans to add three 3nm fabs, one each in Taiwan, Arizona and Japan, to support a multi-year pipeline of demand for the node. The company is working to bring up the new Japan fab as quickly as possible as it seeks to narrow a wide gap between demand and supply.Taiwanese authorities have approved TSMC's upgraded plan to manufacture 3nm chips at its second Kumamoto fab. Japan's Ministry of Economy, Trade and Industry described domestic 3nm production as meaningful for the country's economic security, while saying details of additional government support remain under discussion.
The move comes as TSMC expects the global semiconductor market to exceed US$1.5 trillion by 2030, with AI and high-performance computing accounting for 55%. HPC already represented 66% of the company's second-quarter 2026 revenue.
TSMC also raised its 2026 capital budget to US$60-64 billion amid strong demand for leading-edge technologies. About 10%-20% will go to advanced packaging, testing, mask making and other areas.
Sources: EE Times Japan; TSMC; compiled by DIGITIMES Asia
Packaging strengthens Japan's supply-chain role
Japan's growing importance is particularly visible in advanced packaging, where local suppliers have established strengths in substrates, interposers, semiconductor materials and equipment.TSMC's 3DIC research center in Tsukuba initially worked with about 40 Japanese companies. That number has grown to roughly 120, creating a larger local network for materials evaluation and joint development of next-generation packaging technologies.
Package dimensions are increasing at the same time. Customer products have already reached the 5.5-reticle scale, while TSMC is now producing 5.5-reticle CoWoS and plans a 14-reticle version for 2028 capable of integrating about 10 large compute dies and 20 HBM stacks. The roadmap extends beyond 14 reticles in 2029, alongside a 40-reticle SoW-X system.
TSMC has projected CoWoS capacity to grow at a compound annual rate of more than 80% from 2022 to 2027. As packages become larger, production based on round wafers could eventually become less efficient, potentially creating a longer-term case for panel-type substrates.
The shift could play to Japanese suppliers' strengths in substrates and packaging materials. TSMC's Tsukuba program has focused on areas including large-area package substrates, high-density packaging materials, thermal management, warpage control and fine-pitch interconnects.
Image sensors broaden Japan strategy
Japan is also becoming more important to TSMC in higher-value mature-node segments. The company is increasing capacity through JASM Fab 1 for CMOS image sensor applications, even as demand remains weaker across many commodity mature-node products.That strategy could deepen through Sony Semiconductor Solutions. The companies signed a non-binding memorandum of understanding in May for a proposed strategic partnership covering the development and manufacturing of next-generation image sensors.
Under the proposal, they intend to establish a joint venture in which Sony would be the majority and controlling shareholder, with development and production lines at Sony's new fab in Koshi City, Kumamoto Prefecture. The JV remains subject to a definitive legally binding agreement and customary closing conditions.
TSMC's overseas expansion was initially driven by long-term customer demand rather than geopolitics, although customers increasingly value geographically diversified supply. Its Japanese design center and Kumamoto manufacturing operations are designed to serve customers globally rather than function as a Japan-only network.
Together, these moves are broadening Japan's place in TSMC's global network across leading-edge manufacturing, advanced packaging R&D, design support and image sensors.
Article edited by Jack Wu