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Munich, Germany – 18th August 2026 - The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced its keynotes for this year’s event on November 17th and 18th at the Holiday Inn Munich. Professor Hussam Amrouch, Technical University of Munich, will discuss the AI talent gap and Antoine Madec, Director of Verification, Axelera AI, will explore ‘Pragmatic Verification’.
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Professor Amrouch’s keynote is entitled; ‘AI for Chips, Chips for AI — and the Growing Talent Gap in Between’. It will explore the two-way revolution between AI and semiconductors. On one side, novel AI chips and brain-inspired computing can enable ultra-efficient training and inference at the edge. On the other side, AI is becoming essential for designing future chips, especially as scaling approaches the sub-3 nm era and physical and reliability limits become profoundly critical. The keynote will also address a major bottleneck: the growing talent gap. Through the Munich Center for AI Chips (MACHT-AI) Professor Amrouch will show how training the next generation of engineers in advanced chip technologies is essential for Europe’s future in AI hardware.
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Antoine Madec will present; ‘Perfection Is a Bad Idea: Pragmatic Verification of Complex ASICs at a Scale-Up’ and he will guide the audience through what it really takes to verify a complex ASIC when perfection is off the table. Verification is often presented as a discipline that, with the right methodologies and tools, can be driven all the way to completeness - yet the reality of a scale-up tells a different story, where complex SoCs, ambitious time-to-market, and limited resources force us to make sensible trade-offs Drawing on that experience, Antoine will examine where verification effort truly pays off and where the pursuit of completeness delivers diminishing returns, and he will ask the practical question at the heart of every project: what are the best bang-for-the-buck ways to achieve reliable verification?
“Our keynotes this year will explore two highly important and topical areas, and we expect a very high level of interest from all in our industry,” said Martin Ruhwandi, general chair of DVCon Europe.
Hussam Amrouch is the Professor heading the Chair of AI Processor Design at the Technical University of Munich. He is the Founding Director of the Munich Advanced-Technology Center for AI Chips (MACHT-AI); Academic Director of TU Munich Venture Lab for Semiconductor and Quantum, and also the head of the Brain-inspired Computing at the Munich Institute of Robotics. He has over 330 publications to his name and his research interests are AI chips, design for reliability, advanced and emerging technologies.
Antoine Madec is Director of Verification at Axelera AI, where he leads ASIC verification for next-generation AI accelerator chips. With over 15 years of experience spanning both sides of the Atlantic, he has held roles as technical lead, manager, and applications engineer at companies including Microsoft Xbox, Tesla, Ampere, and Bosch. Antoine specializes in system-level verification and the development of emulation platforms, with a practical philosophy centered on simplicity and efficiency over complexity. At Axelera AI, he drives verification strategy across multiple tape-outs, from architecture through silicon bring-up.
Registration for the event is now open at: https://dvcon-europe.org/registration with reduced rates until October 18th.
ABOUT DVCON EUROPE
The Design and Verification Conference & Exhibition in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, and one of several DVCon events around the globe, DVCon Europe brings chip architects, design & verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design. For more details, visit www.dvcon-europe.org. Follow #dvconeurope on X.
DVCon around the world:
ABOUT ACCELLERA SYSTEMS INITIATIVE
Accellera Systems Initiative (Accellera) is an independent, not-for profit organization, dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit accellera.org. For membership information, please email membership@accellera.org. Follow @accellera on Twitter or to comment, please use #accellera.
ACCELLERA GLOBAL SPONSORS: Cadence; Siemens; Synopsys
# # #
Accellera Systems Initiative and DVCon are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.
More Info
Munich, Germany – 18th August 2026 - The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced its keynotes for this year’s event on November 17th and 18th at the Holiday Inn Munich. Professor Hussam Amrouch, Technical University of Munich, will discuss the AI talent gap and Antoine Madec, Director of Verification, Axelera AI, will explore ‘Pragmatic Verification’.
View attachment 5088
Professor Amrouch’s keynote is entitled; ‘AI for Chips, Chips for AI — and the Growing Talent Gap in Between’. It will explore the two-way revolution between AI and semiconductors. On one side, novel AI chips and brain-inspired computing can enable ultra-efficient training and inference at the edge. On the other side, AI is becoming essential for designing future chips, especially as scaling approaches the sub-3 nm era and physical and reliability limits become profoundly critical. The keynote will also address a major bottleneck: the growing talent gap. Through the Munich Center for AI Chips (MACHT-AI) Professor Amrouch will show how training the next generation of engineers in advanced chip technologies is essential for Europe’s future in AI hardware.
View attachment 5089
Antoine Madec will present; ‘Perfection Is a Bad Idea: Pragmatic Verification of Complex ASICs at a Scale-Up’ and he will guide the audience through what it really takes to verify a complex ASIC when perfection is off the table. Verification is often presented as a discipline that, with the right methodologies and tools, can be driven all the way to completeness - yet the reality of a scale-up tells a different story, where complex SoCs, ambitious time-to-market, and limited resources force us to make sensible trade-offs Drawing on that experience, Antoine will examine where verification effort truly pays off and where the pursuit of completeness delivers diminishing returns, and he will ask the practical question at the heart of every project: what are the best bang-for-the-buck ways to achieve reliable verification?
“Our keynotes this year will explore two highly important and topical areas, and we expect a very high level of interest from all in our industry,” said Martin Ruhwandi, general chair of DVCon Europe.
Hussam Amrouch is the Professor heading the Chair of AI Processor Design at the Technical University of Munich. He is the Founding Director of the Munich Advanced-Technology Center for AI Chips (MACHT-AI); Academic Director of TU Munich Venture Lab for Semiconductor and Quantum, and also the head of the Brain-inspired Computing at the Munich Institute of Robotics. He has over 330 publications to his name and his research interests are AI chips, design for reliability, advanced and emerging technologies.
Antoine Madec is Director of Verification at Axelera AI, where he leads ASIC verification for next-generation AI accelerator chips. With over 15 years of experience spanning both sides of the Atlantic, he has held roles as technical lead, manager, and applications engineer at companies including Microsoft Xbox, Tesla, Ampere, and Bosch. Antoine specializes in system-level verification and the development of emulation platforms, with a practical philosophy centered on simplicity and efficiency over complexity. At Axelera AI, he drives verification strategy across multiple tape-outs, from architecture through silicon bring-up.
Registration for the event is now open at: https://dvcon-europe.org/registration with reduced rates until October 18th.
ABOUT DVCON EUROPE
The Design and Verification Conference & Exhibition in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, and one of several DVCon events around the globe, DVCon Europe brings chip architects, design & verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design. For more details, visit www.dvcon-europe.org. Follow #dvconeurope on X.
DVCon around the world:
- - DVCon India – September 1st to 3rd, 2026
- - DVCon Taiwan – September 8th, 2026
- - DVCon Japan – September 10th, 2026
- - DVCon Europe – November 17th and 18th, 2026
- - DVCon US – March 1st to 4th, 2027
ABOUT ACCELLERA SYSTEMS INITIATIVE
Accellera Systems Initiative (Accellera) is an independent, not-for profit organization, dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit accellera.org. For membership information, please email membership@accellera.org. Follow @accellera on Twitter or to comment, please use #accellera.
ACCELLERA GLOBAL SPONSORS: Cadence; Siemens; Synopsys
# # #
Accellera Systems Initiative and DVCon are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.
More Info