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  1. F

    Intel CEO Lip-Bu Tan Reportedly Moves Up 14A Risk Production To Q1 2027, As The Node’s Defect Density Races Toward Target

    I'd be interested to see if/how they figure die height into the chip design.
  2. F

    Samsung's Q3 profit seen jumping nine-fold, but chip margins may be flat

    Expectations again.
  3. F

    Qualcomm Licenses Patents on Huawei’s LogicFolding Chip Tech

    On October 5, Huawei officially announced that it had reached a multi-year, broad-ranging patent licensing agreement with Qualcomm. The agreement includes cross-licensing of patent portfolios in multiple fields such as 5G, computing, artificial intelligence, and networking, as well as Qualcomm’s...
  4. F

    Qualcomm Licenses Patents on Huawei’s LogicFolding Chip Tech

    (Bloomberg) -- Qualcomm Inc. has agreed to license patents underpinning Huawei Technologies Co.'s novel LogicFolding chipmaking technique, a win for the Chinese company and its push to advance in overseas AI markets. The multiyear deal is part of a cross-license agreement between the two...
  5. F

    Intel CEO says Intel can serve only 50% of customers, attributes to CPU demand

    Yes, this was not expected. Possibly not enough DRAM, so they cannot build enough PCs with Intel CPUs? So I felt Tan's explanation was not exactly spot on. It should be that supply constraints are hampering PC builds. Still, near the end of the article, it's implied that Intel's assuring...
  6. F

    Intel CEO says Intel can serve only 50% of customers, attributes to CPU demand

    Intel is struggling to produce enough processors to meet surging demand, with CEO Lip-Bu Tan saying the company can currently supply only about half of what its customers are asking for. “CPU demand is so high that we can only supply 50% of customers,” Tan said during a conversation with Cisco...
  7. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    I appreciate what you are saying, I think the burden is on Intel to clarify this more, unless they already have in some IEEE publication we have not come across yet. It might be trivial, but just wondering, for example, are there no transistors in between the blocks? Or can more transistors be...
  8. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    I think it would be clearer if they show side by side the PowerVia connection and the original Frontside-only layout. The implication of area penalty is at odds with density improvement claims. The distance between blocks of cells would have to be reduced. Were there power/ground lines there?
  9. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    I think Intel isn't so clear and sometimes apparently self-contradictory on these important claims:
  10. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    I had understood that graph to compare different numbers of poly/M1 pitches. The BSPDN had the smallest number it seemed, implying fewer transistors in that block.
  11. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    I don't know if SRAM is counted in Bohr's formula. The paper refers to compaction in the SRAM periphery. The block-level area compaction came from wirelength reduction, so it certainly reduces area, but shouldn't affect density.
  12. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    The BSPDN density increase should be built into the reduced cell height, since the power/ground rails are removed.
  13. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    The scale bars shouldn't be the same, Intel 18A has the larger M0 pitch.
  14. F

    Intel Panther Lake Teardown Taking a look inside Intel’s latest consumer chip and 18A process node

    I like how they tied elemental composition findings to the process.
  15. F

    TSMC A14 at 2026-Dec-IEDM

    So, to confirm, A14 has no backside power?
  16. F

    CXMT Announces new G5 platform enters mass production

    This is essentially 1b-level, very impresssive. Just one node behind the leading edge (1c/1-gamma).
  17. F

    Intel 18A yield, PC Panther Lake vs DataCenter Clearwater Forest

    It's a consistent explanation, but it wasn't ServeTheHome who left out "area" but Intel themselves.
  18. F

    Intel 18A yield, PC Panther Lake vs DataCenter Clearwater Forest

    I guess their assumption was 29% of compute dies had defects in the recoverable area?
  19. F

    Intel 18A yield, PC Panther Lake vs DataCenter Clearwater Forest

    Wildcat Lake (essentially a smaller Panther Lake) has recovery of 29% of compute dies for current SKUs. https://www.servethehome.com/intel-core-series-3-wildcat-lake-cpu-at-hot-chips-2026/
  20. F

    Is DRAM also moving from planar to 3D? Samsung and SK Hynix are taking the lead, and the next wave of equipment demand is emerging

    September 16, 2026, 17:12 - Youxia Industry Data Center September 16, 2026 (YouAnalysis/Industry Data Center Report) — In the past, increasing DRAM capacity mainly relied on continuously shrinking the process to fit more memory cells into chips of the same size. However, as the size becomes...
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