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Amiq EDA Wiki

Established in 2008 as an EDA software company. We have encountered three recurring challenges during our consulting work: developing new code to meet tight schedules, understanding legacy or poorly documented code, and getting new engineers up to speed quickly. In the software world, Integrated Development Environments (IDEs) are commonly used to overcome such challenges. At the time, no IDE was available for hardware design and verification specific languages like Verilog, VHDL, e Language or SystemVerilog. In 2005, we seized the opportunity and started to develop an IDE for our internal use, and in 2006 we officially launched the beta version, which received an excellent feedback. In 2008 AMIQ EDA was founded, as a spin-off from AMIQ Consulting, and we released the DVT Eclipse IDE, the first IDE for design and verification on the market.

The EDA Design & Verification Tools:

DVT Eclipse IDE

Design and Verification Tools (DVT) is the first integrated development environment (IDE) for the e language, SystemVerilog, Verilog, Verilog-AMS, and VHDL. The DVT Eclipse IDE is built on the Eclipse Platform and is similar to well-known programming tools like Visual Studio and IntelliJ. See more

Verissimo SystemVerilog Testbench LinterVerissimo is a static code analysis tool that allows engineers accurately identify SystemVerilog language pitfalls, semantic, style or performance issues, dead or duplicate code, and enforce compliance with verification methodologies like UVM or company specific code writing guidelines. See more

Specador Documentation Generator
Specador automatically generates accurate HTML documentation from SystemVerilog, Verilog, VHDL and e Language source code, based on effective compilation and comments analysis. It enables design and verification engineers to effortlessly generate and maintain proper and well-organized documentation. See more

DVT Debugger
The DVT Debugger is an extended capability of the DVT Eclipse IDE, which provides advanced debugging capabilities for the e language, SystemVerilog, Verilog and VHDL users and enables them to perform debugging from the same place where they develop their code, therefore, reducing debug flow complexity. See more

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