Will EDA Evolve into a Foundry/Platform/AI/ML Model? Ramifications?

[Arthur Hanson]

Just like TSM and others have followed a foundry model, will EDA do the same. Rather than develop designs using EDA, what would happen if EDA firms followed a foundry model and have customers just spec out requirements on a platform and let the EDA firm itself design the semi? Just like TSM changed the semi landscape with using the foundry model to build semis, EDA firms could further automate their platforms to go from just aiding in chip design to actually designing chips to customer specifications. This model could offer the same scale of efficiencies as the foundry model in producing chips, by greatly leveraging the use of IP over a much broader base, just like the foundry? With AI/ML and platforms becoming ever more sophisticated this would become far more efficient model as far as talent, time and financial resources. TSM without any doubt has proved the immense power of the foundry model in the tech world and there is no reason this model should not be extended to EDA, the benefits are to great. The merger of the very, very well proven foundry and platform models that AI/ML will be critical in their making is all about increasing resource utilization that has the power to change the semi world, but everything else. The combination of these two forces could change the world as we know it, from education, training, finance and application. Much of these processes has already been proven and it isn't if it will happen, but when and it what form. TSM is able to serve multiple customers with out conflict, so there is no reason the foundry model could not be extended to complete design. Also just as TSM has vastly increased the efficiency and speed of the industry, the same could be done with extending EDA beyond its current boundaries. TSM has already proved the massive power of the platform/foundry model, it is now time to apply it to literally everything else, for combining the foundry model with AI/ML and advanced memories will change almost everything in the world as we know it, it isn't a matter of if, but when. Since I last wrote on this subject AI/ML and memory all have advanced dramatically even further enabling these trends and opportunities. This is all part of the " The Great Acceleration" that I have written about in the past. Comments, thoughts and additions solicited and welcome.


additional note, this would radically change education, training, business/finance and the very structures our societies have been built on for years at a speed most of the world would have radically change to adapt to. Uses would have to found for the massive amount of resources this would free up. This process could change radically almost every human endeavor we are engaged in. Morris Chang is one of the great geniuses of our time.

 

[Daniel Payne]

Arthur, what you propose is already being done by IC Design Services companies. In the past, many of the EDA companies also had an IC Design Services department, and Cadence was the most noticeable in building up what their Spectrum Services Group. There are probably 100+ IC Design Services providers, and some of them are listed here on SemiWiki at https://semiwiki.com/category/semiconductor-services/. I worked at a company called Silicon Compilers, Inc. and they designed the first generation MicroVax I chip for DEC using their own EDA tools and layout generator technology. At Synopsys they have a very large physical IP group and they use Synopsys IC tools as well.

 

[Arthur Hanson]

Arthur, what you propose is already being done by IC Design Services companies. In the past, many of the EDA companies also had an IC Design Services department, and Cadence was the most noticeable in building up what their Spectrum Services Group. There are probably 100+ IC Design Services providers, and some of them are listed here on SemiWiki at https://semiwiki.com/category/semiconductor-services/. I worked at a company called Silicon Compilers, Inc. and they designed the first generation MicroVax I chip for DEC using their own EDA tools and layout generator technology. At Synopsys they have a very large physical IP group and they use Synopsys IC tools as well.

Dan, to what degree was the process automated and what level of automation do you see in the future? I know in drug design they had robotic systems actually make discoveries on their own with no human intervention during the process. When will we be able to give a system the end functions desired and a complete design comes out with minimal intervention or intervention at a much lower level?

 

[Tanj]

Arthur, what are you proposing that is new? The delivery is generally what comes out of the foundry. Companies like Xilinx, Broadcom, Marvell, Microchip, Infinineon, NXP - these all have businesses ready to work with clients to define custom chips. TSMC and Samsung will do that too, if you don't mind being committed to them. You can find a team with relevant experience at putting a whole ASIC together which may include various functional elements outside the wheelhouse of the client. If you want to stick to what you do best, interviewing these guys may land you a team which rounds out the parts of the chip which are essentially off the shelf, plus experience in integration, tools, validation, and probably a known schedule for wafers at the foundries. That said, you need to bring your own A-team for your own IP and you will feel pain if you do not invest in the integration and validation for yourself (trust but verify).

How do the EDA companies bring something different and better here? It is a competitive, wide ecosystem already.

 

[Arthur Hanson]

I guess I wasn't being clear. At what point will thfe process be automated to the point a single person could specify the results they wanted and the process would be automated from there on without the direct use of a team, although the program would be initially written by a team. The idea is to massively leverage a team once so they can be replicated by a program/platform without further intervention required. This is already being done in many applications and industries in highly complex fields like pharmacology, chemistry and others. If this can't be done, what different obstacles prevent it over other fields achieving it? I am an outsider and trying to understand why this can't be done with semis.

 

[Daniel Nenni]

If you want to learn about the future of EDA I suggest you check out the SNPS investor call. Aart de Geus is the reigning EDA CEO champion and worth listening to, absolutely.

Synopsys, Inc. | Investor Relations & Investor Resources

Get the latest Synopsys investor relations information from Synopsys earnings, financial news, events, webinars, & stock information. Subscribe Now.

www.synopsys.com

If you want to discuss that let me know...

 

[Daniel Payne]

Arthur, the closest thing to quick chip design today would be with the FPGA vendor tools, IP and flow: Xilinx (Vivado Design Flow) and Intel (Intel HLS Compiler). With an FPGA the designer is removed quite a bit from the physical Implementation, yet they still have to choose their IP building blocks and model with an RTL language or a bit higher level using High Level Synthesis, even so they likely end up doing some floor planning to get the best PPA. In the future, maybe decades from now a single person could say, "Hey Alexa, design me a WiFi Router System", but we aren't anywhere near that today.

 

[Tanj]

As Daniel says, FPGA is about the closest to this. There are also schemes like the ARC processor from Synopsys where an iterative process of refinement can take a conventional program and refine it into an optimized core with extended instructions which can drive acceleration logic, which you figure out by profiling the runs and looking for significant work that is suitable to accelerate. Still, you have to know your tools. FPGA has tradeoffs in clock rate, interconnect, and the way SRAM and hard-blocks are provided that reward you for a particular style of code. That might not be the best thing to do with a fully custom ASIC, which generally has more gates, more flexibility, and higher clocks. And it can be very different to design silicon than to write code, since the degrees of parallel in hardware have no easy equivalent in normal programming. There are programming languages which can express parallel - and verilog/RTL are examples - they are not much used by programmers since they do not work efficiently on CPUs which have very limited and rigid forms of parallel operation. So, there is no substitute for understanding the capabilities of the medium.

There are examples of work done by one person in reasonable time. Some of the work done at universities around RISC-V have taken just a few person-months to generate custom silicon. Projects of reasonable size, with some supporting IP libraries.

Part of the reason for large teams is the need to be perfect. Modern chips have expensive masks and long turn around times, so there is a huge premium upon perfection. Teams can easily spend more on verification than upon design. Hiring a team with a track record can smooth the way on a one-off project, and a lot of chips are one-offs. You can also have a lot of off the shelf IP to understand and integrate for you IO, your command queues, your production test structures, and for security. Those are, not surprising, things which generally come hard-coded as periphery to a modern FPGA.

 

[Arthur Hanson]

Thanks to everyone that responded, I definitely have some homework to do. I see the automation of everything from scientific concept to finished product and even marketing and distribution coming on like a speeding freight train. All phases of just about everything are picking up speed and the individuals and organizations that master these changes will have to leverage themselves to help others for the potential for societal and government trauma are great and with knowledge and power come responsibility and wisdom. Changes that this trend are coming on with such speed and breadth, that if not handled properly the damage could be greater than the promise. Technology is not just about science, but applying it to benefit society and the ecosystem we all live in. Thanks again and any thoughts or comments on this end of the equation will be appreciated, since all of you have an inside view.

 

[Tanj]

Be careful to distinguish delivery from speculative execution. The hype always seems like things are happening at breathless speed. The number of parts which really do deliver, and get delivered, is much slower, even tedious. Getting things right when you have a billion elements on an everyday chip is hard. Realizing an advantage in the market when it is 2 to 3 years between launching the RTL work (and that may be much after launching the idea) until tapeout, sample production, debug and verify, actual production, stable use in a product - often the market has moved on to some other product or simply the market evaporated due to changes in how people get things done or what they are interested in.

It sure would help to have a much shorter cycle. That would reduce the speculative losses, and should reduce costs. Might be more interesting to look for that on trailing edge technologies, since leading edge like EUV certainly is not reducing pipeline length or rule complexity. Logically those older process lines could get a mid-life kicker in EDA to make it cheaper to put innovative products through well known and mature processes.

 

[Arthur Hanson]

Thanks everyone, all of you have given me areas of further study and this is what's great about SemiWiki, it's definitely a great source of collaboration and information exchange. I study over a much broader area, but obviously not with the depth of people in each field, but I do connect the dots many times, but not all.