What's the current trajectory for predictions of power density limits on new chips?

[Xebec]

Hi folks -

For many years there have been predictions that silicon chips will hit a wall on thermal density that cannot be solved by conventional cooling solutions. Items like local hot spots, and not just total power draw come into play reducing the maximum heat output that a die can remain stable. Yet, it appears CPUs and GPUs (for example) are still increasing the amount of power output per mm2 of die/wafer.

For example, on Samsung 8nm - Nvidia has GPUs now approaching 1 watt per mm2 (3090Ti), as compared to about half of that 5 years ago (NVidia Titan X). The CPU side is similar -- Alderlake on desktop (12900K-KS) pushing 240-270W in some workloads on a ~215mm die, vs. the previous "power hog" AMD FX-9590 using 220W on a 315mm die back on 32nm.

What's the current status of this?, and what are some thermal density limits that we really cannot exceed? Will that limit of watts per mm2 reduce as transistors get smaller?

Thanks!

 

[IanD]

It's all a matter of how much effort (and money) you're willing to put into cooling, specifically packaging and liquid cooling for high power density devices. 1W/mm2 isn't actually that much, for high-speed high-activity circuits we see far higher power density than this in small hot areas (surrounded by cool ones) with very high clock rates (tens of GHz) and the circuits themselves (transistors and metal) don't have a problem with this, the problem is getting the heat out, usually from the back of the die.

Silicon is a pretty good thermal conductor (150W/mK), so for a typical thickness die (700um) the circuits only run about 5C hotter than the back of the die at 1W/mm2 -- if the die is thinned, less than this. The problem then is getting the heat away from the silicon, especially if there are any non-metallic thermal interface materials (TIM) in the way -- for example the indium-silver solder used by Intel and others between die and package lid is about 80W/mK, silver-filled resin/silicone/eopxy are less than 10W/mK, and there's then usually another layer of TIM between package lid and heatsink, even if this is water-cooled.

If you go to exotic cooling solutions like liquid-cooled microchannels on the back of a thinned die then the sky is the limit, but these have only been used experimentally or in ludicrously expensive systems (e.g. IBM).

So it's not really a problem for the chip, it's a problem for packaging and cooling and how much you're willing to spend on it ;-)