Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/what-is-the-minimum-viable-size-of-a-new-300-mm-fab.17382/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

What is the minimum viable size of a new 300 mm fab?

mozartct

Active member
I need help from the community for an upcoming event (ASMC).

Considering the cost of land, of equipment etc. what would be the size of a generic competitive logic foundry being built today? TSMC is often confusing the issue by not calling each fab complex with its own name. So you end up with Fab14P8 but if you were next to P8, you would call that a self-enclosed factory located next to a similar one called P7 etc

I am looking for an estimate in "300 mm wafer-start per month". I am thinking it's in the neighborhood of 120,000 units or about 4k per day. Is that a good rule of thumb?
 
I need help from the community for an upcoming event (ASMC).

Considering the cost of land, of equipment etc. what would be the size of a generic competitive logic foundry being built today? TSMC is often confusing the issue by not calling each fab complex with its own name. So you end up with Fab14P8 but if you were next to P8, you would call that a self-enclosed factory located next to a similar one called P7 etc

I am looking for an estimate in "300 mm wafer-start per month". I am thinking it's in the neighborhood of 120,000 units or about 4k per day. Is that a good rule of thumb?
TSMC AZ phase 1 and 2 are supposed to be 600K per year. Per fab that is 25k per month (or 833 per day). Samsung's new texas fab for 3GAP family is a bit smaller than each AZ phase. The samsung fab has 80% the workers and 85% the investment (my guess is around 20k per month). My gut says this is either at or near the floor for a new leading edge 300mm fab on a new plot of land. If it is an expansion to an existing site then I think you should be able to get away with a 15k WSPM expansion without much issue.
 
That's smaller than I thought. TSMC 15P1 and P2 seemed much larger than 850 wpd each but i could be wrong. The total # of steps is another important variable. Total wafer-steps may be a more accurate way to think about it. If I do 5 nm, I have more steps than 28 nm so I will be able to output fewer wafers per day within the same footprint.
 
That's smaller than I thought. TSMC 15P1 and P2 seemed much larger than 850 wpd each but i could be wrong. The total # of steps is another important variable. Total wafer-steps may be a more accurate way to think about it. If I do 5 nm, I have more steps than 28 nm so I will be able to output fewer wafers per day within the same footprint.
Yeah 15P1/2 are not big. By TSMC sizing they are actually kind of small, and by the standard of some of those monster Samsung fabs in Korea they are puny. A simpler node like 28nm could have higher throughput per sq ft than N5 and especially N3, but it won't scale linearly.
 
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So one could get by at 1000 wafers per day BUT in reality, it would need to be larger to be competitive. This reminds me of the new Bosch fab in Dresden. Very small and probably not cost effective BUT good leverage when negotiating with Infineon or anyone else.

Agreed on non-linearity of mask-level per node since many additional cleaning steps are used at the finer linewidth.
 
So one could get by at 1000 wafers per day BUT in reality, it would need to be larger to be competitive. This reminds me of the new Bosch fab in Dresden. Very small and probably not cost effective BUT good leverage when negotiating with Infineon or anyone else.

Agreed on non-linearity of mask-level per node since many additional cleaning steps are used at the finer linewidth.
There are also a number of steps that don't increase in complexity by much as you go to new nodes (eg poly upper/middle BEOL/MIM caps), and the fact that something like N3 doesn't have like 8x the number of metal layers like you would expect if process complexity scaled linearly.
 
Good point, thanks.

To summarize, we have # of wafers, yield, # of steps and linewidth. Competitive foundry would need to optimize the first 3 (leaving litho aside for now). So I want the yield to be as high as possible with the least # of steps (not too many cleans for example), making sure that the fab is as big as practical without compromising the other 2.
 
Good point, thanks.

To summarize, we have # of wafers, yield, # of steps and linewidth. Competitive foundry would need to optimize the first 3 (leaving litho aside for now). So I want the yield to be as high as possible with the least # of steps (not too many cleans for example), making sure that the fab is as big as practical without compromising the other 2.
Uniformity is a big part of the equation as well (both within wafer and wafer to wafer).

Cleans are not something to skimp on either because they are aren't too expensive and improve DD and uniformity. Multiple node flavors with VTs and metal stacks that are optimized for different markets is another big plus. Besides cost velocity is another important metric.

To further add on, number of step reductions isn't always good. A super obvious example of this is you wouldn't replace a SADP layer with a direct print EUV layer, heck back in say 2017 you wouldn't even replace a SAQP or LE^3 layer with EUV. Another litho example Fred is fond of is with N5 TSMC used EUV double for one layer whereas Samsung just pushed single exposure to the max at 5/4LPE. On paper you would think that Samsung's approach was better. But in practice they turned up the dose so high and resolution so close to the redline that throughput and DD suffered. Layer counts and process complexity have to be balanced against DD, uniformity, PPA, and throughput.
 
Excellent feedback. You placed me on another related track. The transit time to go between tool A and tool B is another important metric. Adding steps increases that time and making the fab infinitely large would also increase that transit time.

Like everything in our business, it's delicate and complicated.
 
You placed me on another related track. The transit time to go between tool A and tool B is another important metric. Adding steps increases that time and making the fab infinitely large would also increase that transit time.
Why? That assumes that, say, all the lithography tools are together and all the etch tools are together, etc. Why not distribute them appropriately
 
Because you have other tools in between the tools and because fo dispatching with re-entrant flows. Example of tool between tools: CD-SEM or cleaning tools. You are trying to minimize the overall travel time on average. Say you go from Litho to PVD to Plating to CMP to Clean, the position (distance) between each tool will matter. So some optimizing would be needed though there are other constraints such as bulk distribution of slurries, time between PVD and plating etc.

Now if I blow up the fab (beyond optimized size), i will encounter issues with optimized dispatching. On paper, I laid out the fab to go to litho A in one corner and then PVD A but because the tool is busy or down, I now need to go to litho B, located far away... you can see how that would cause diminishing returns.
 
Because you have other tools in between the tools and because fo dispatching with re-entrant flows. Example of tool between tools: CD-SEM or cleaning tools. You are trying to minimize the overall travel time on average. Say you go from Litho to PVD to Plating to CMP to Clean, the position (distance) between each tool will matter. So some optimizing would be needed though there are other constraints such as bulk distribution of slurries, time between PVD and plating etc.

Now if I blow up the fab (beyond optimized size), i will encounter issues with optimized dispatching. On paper, I laid out the fab to go to litho A in one corner and then PVD A but because the tool is busy or down, I now need to go to litho B, located far away... you can see how that would cause diminishing returns.
Sure, but at some point in size don't you have to split a fab into "sub-fab" sections where each one is optimized, and 99%+ of the transport is within each section, but they can take advantage of the economy of scale by sharing staff / supplies / occasional capacity balancing?
 
That's where P1, P2 etc. come in. You have effectively separate factories sharing staff and utilities. I think that logic and memory have different optimum sizes BTW.
 
They do. Memory fabs are much higher capacity per sq ft, have a different tool mix, and obviously far fewer BEOL layers.
 
To the original question there are 2 key factors in determining the size of a fab. 1-operational labor cost, 2-technology node. In high cost markets such as the US it takes nearly 1M wpy to largely offset the cost of operation labor vs. the capital investment. One can never close the gap to lower cost geographies, but an analysis in these pages a few months ago suggested at full scale TSMC's manufacturing cost in AZ would be less than 10% higher than Taiwan. Second technology node. Older nodes are fewer layer and less complexity between layers so to achieve 1M wpy requires less phyiscal space than the leading edge nodes. One project I worked on we estimated needing about 1M sqft at 7nm to achieve 1M wpy capacity. At 2nm based on historical node to node scalars, US based manufacturing would need >1.5M sqft to achieve that. My editorial note is that Intel's Ohio project is less than half the size it needs to be if they intend to be cost competitive with TSMC on the leading edge nodes.
 
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