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TSMC’s Leading-Edge Fab Investments Set Stage for Sale Surge in 2H19

Daniel Nenni

Admin
Staff member
World’s largest foundry benefits from increasing demand and tight supplies of 7nm devices.

Taiwan Semiconductor Manufacturing Company’s heavy investments in advanced wafer-fab technology are set to pay off significantly for the world’s largest silicon foundry as it continues the production ramp of 7nm ICs in the second half of this year, according to an analysis in IC Insights’ September Update to the 2019 McClean Report.

Figure 1 provides an updated outlook for TSMC’s 2019 sales using quarterly revenue reported by the foundry in first half of this year and IC Insights’ projection for the second half. As shown, the company has estimated its current full-year sales to be about flat with 2018, but its 2H19/1H19 sales are forecast to jump by 32%—more than three times the 10% growth rate expected for the entire IC industry in the second half of 2019, based on IC Insights’ projection. There is little doubt that 7nm application processors for new smartphones from Apple and Huawei are driving the forecast for a strong second-half rebound in TSMC’s sales.


Figure 1

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have over 7x the dollar volume sales at <40nm processes as compared to the combined 2019 total of GlobalFoundries, UMC, and SMIC ($22.9 billion versus $3.2 billion). SMIC entered initial production of 28nm technology in 4Q15, more than three years after TSMC began fabricating wafers with its 28nm process. SMIC expects to log recognizable revenue from its new 14nm FinFET technology sometime in the fourth quarter of this year (and introduce 12nm FinFET technology in 2020), once again about three years behind TSMC’s introduction of similar processes.

In 2019, TSMC is expected to have 66% of its sales come from <40nm technology. Moreover, IC Insights is forecasting that TSMC will have $8.9 billion in 7nm revenue this year (Figure 2), representing about 26% of its total sales in 2019 and 33% of its 4Q19 revenue (thanks to customers Apple and Huawei)!


Figure 2

The pace at which TSMC’s customers adopt leading-edge process technologies has quickened, as well. It took eight quarters for the foundry’s 40-45nm technology to secure greater than 20% of its total sales, five quarters for its 28nm process to exceed that threshold, and only three quarters for its 7nm process to account for more than 20% of its quarterly revenue. In fact, TSMC’s 20nm, 14nm, and 10nm technologies all surpassed 20% of its total sales within three quarters. Amazingly, the company believes that its ramp of 5nm technology, as a percent of its sales, will be even faster than its 7nm process! Strong demand for the advanced nodes has resulted in tight supply and longer lead times. As a result, TSMC is already planning to set aside more funds to expand capacity for its advanced processes.

Report Details: The 2019 McClean Report
Additional details on semiconductor foundry trends are provided in the August and September Updates to The McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry. A subscription to The McClean Report includes free monthly updates from March through November (including a 200-page Mid-Year Update), and free access to subscriber-only webinars throughout the year. An individual-user license to the 2019 edition of The McClean Report is priced at $4,990 and includes an Internet access password. A multi-user worldwide corporate license is available for $7,990.

To review additional information about IC Insights’ new and existing market research reports and services please visit our website: www.icinsights.com.

PDF Version of This Bulletin
A PDF version of this Research Bulletin can be downloaded from our website at http://www.icinsights.com/news/bulletins/
 

Daniel Nenni

Admin
Staff member
The TSMC OIP event is tomorrow. Let me know if you have questions to ask. I have 1 on 1s with TSMC executives. And if you are attending please introduce yourself. It would be great to meet you.
 

raghu78

Member
The TSMC OIP event is tomorrow. Let me know if you have questions to ask. I have 1 on 1s with TSMC executives. And if you are attending please introduce yourself. It would be great to meet you.
Daniel
If its possible can you ask the following questions

1. What are the key specs of N5 and N5 HPC . Minimum Metal Pitch, Contacted Poly Pitch, Track height . Transistor Logic density, SRAM cell size .

2. Does TSMC N5P have an increase in logic density vs N5 ?

3. Does TSMC N3 use FINFET or GAA FET ?

4. When is TSMC N3 expected to be in HVM ?

I know you will not get answers to most of these questions. But please try and ask these questions.
 

Arthur Hanson

Active member
Dan, do you have any information on TSM's effort in MEMS, which Morris Chang said are one of the largest opportunities for the tech sector? Even though on larger nodes, these will require many very advanced and new methods to fabricate. I see the market for very high value and complex mems opening entirely new frontiers in the semi/nanotech sector.
 

Daniel Nenni

Admin
Staff member
Dan, do you have any information on TSM's effort in MEMS, which Morris Chang said are one of the largest opportunities for the tech sector? Even though on larger nodes, these will require many very advanced and new methods to fabricate. I see the market for very high value and complex mems opening entirely new frontiers in the semi/nanotech sector.
I will ask about MEMs strategy.
 

Daniel Nenni

Admin
Staff member
Daniel
If its possible can you ask the following questions

1. What are the key specs of N5 and N5 HPC . Minimum Metal Pitch, Contacted Poly Pitch, Track height . Transistor Logic density, SRAM cell size .

2. Does TSMC N5P have an increase in logic density vs N5 ?

3. Does TSMC N3 use FINFET or GAA FET ?

4. When is TSMC N3 expected to be in HVM ?

I know you will not get answers to most of these questions. But please try and ask these questions.
Will do. Should not be a problem. Others on SemiWiki may already know the answers (Scott Jones).
 

ChrisGar

Member
The pace at which TSMC’s customers adopt leading-edge process technologies has quickened, as well.

Interesting comment given how many in the industry are suggesting that technology node adoption rate will slow down. (e.g.,. GF after stopping 7nm development)

I haven't seen any analysis on this -- but maybe it is possible that both things are true. That is, if you look at TSMC's profile node adaption rate is speeding up ... while at the same time a node like 14/16nm will have a longer volume life in industry. (but someone smarter than me would have do this analysis -- it should be looked at with industry-wide view)
 

Daniel Nenni

Admin
Staff member
Daniel
If its possible can you ask the following questions

1. What are the key specs of N5 and N5 HPC . Minimum Metal Pitch, Contacted Poly Pitch, Track height . Transistor Logic density, SRAM cell size .

2. Does TSMC N5P have an increase in logic density vs N5 ?

3. Does TSMC N3 use FINFET or GAA FET ?

4. When is TSMC N3 expected to be in HVM ?

I know you will not get answers to most of these questions. But please try and ask these questions.
  1. N5 is said to be 30nm M2P and 50nm CPP with 6 tracks and 173MTx/mm2. This works out to ~1.8x denser than N7 which is what TSMC has said. Scott Jones is pretty sure M2P is ~ 30nm and 50nm for CPP which is what is needed to get the 1.8x density improvement they have discussed.

  2. As far as I understand it N5P is the same design rules, just more strain, a performance enhancement. Apple requires a new process every year so this is it. N5P will be out in 2021 for the Apple iProduct refresh. I would expect more optimizations will be announced next year so you may see a density improvement based on better EUV or something like that.
N6 was discussed, still on track for 2020 production. This will be the dominant node moving forward in my opinion, replacing N7 and N7+.
  1. N3 was not discussed but from what I understand it is FinFET based, N2 will be GAA. Samsung

  2. The TSMC process schedule is synced with Apple so N5 in 2020, N5P 2021, and N3 2022, absolutely.
It is interesting to note that TSMC made the claim that N7+ is the "first commercially available EUV process". Samsung announced commercialization of 7LPP in Q4 2018. Samsung announced 3nm is GAA earlier this year. It will be interesting to see who gets GAA into "commercial production first.

Anybody else?
 

Daniel Nenni

Admin
Staff member
The pace at which TSMC’s customers adopt leading-edge process technologies has quickened, as well.

Interesting comment given how many in the industry are suggesting that technology node adoption rate will slow down. (e.g.,. GF after stopping 7nm development)

I haven't seen any analysis on this -- but maybe it is possible that both things are true. That is, if you look at TSMC's profile node adaption rate is speeding up ... while at the same time a node like 14/16nm will have a longer volume life in industry. (but someone smarter than me would have do this analysis -- it should be looked at with industry-wide view)
Apple adopts a new process node every year so Apple competitors must do the same (thus the close partnership Apple has with TSMC). AI and cloud chips will also push the leading edge process technologies but maybe not as quickly. According to Globalfoundries 75% of the semiconductor devices shipping today are based on mature technologies (12nm and above). TSMC numbers jibe with that as well with about 25% of revenues at 10nm and below.
 

Arthur Hanson

Active member
Dan, one more question, how is TSM doing with Crossbar memory. I have heard they are going to use it as onboard memory incorporated into some chips. Will TSM ever also become a memory company? This is the same question I had when we first met in 2013 and I have read some subtle references to TSM and Crossbar, but nothing solid, except as onboard memory in some limited applications. If any company could change the memory game it would be TSM. I imagine the advanced, very dense memory is hard to fabricate as evidenced by the experience of both Intel and Micron trying to work with 3dXpoint. Any views on both would be appreciated.
 

Daniel Nenni

Admin
Staff member
Dan, one more question, how is TSM doing with Crossbar memory. I have heard they are going to use it as onboard memory incorporated into some chips. Will TSM ever also become a memory company? This is the same question I had when we first met in 2013 and I have read some subtle references to TSM and Crossbar, but nothing solid, except as onboard memory in some limited applications. If any company could change the memory game it would be TSM. I imagine the advanced, very dense memory is hard to fabricate as evidenced by the experience of both Intel and Micron trying to work with 3dXpoint. Any views on both would be appreciated.
Have you seen this article?


TSMC uses memory related IP to enable wafer customers only. They do internal development and work with ecosystem partners. I seriously doubt TSMC would change their business model and become a memory company.
 

Arthur Hanson

Active member
Dan, thank you very much for the link, it was very informative and I look forward to more blogs in this area. Do you have any thoughts on whether Micron will is working on advanced memory technologies beyond 3dXpoint?
 

raghu78

Member
  1. N5 is said to be 30nm M2P and 50nm CPP with 6 tracks and 173MTx/mm2. This works out to ~1.8x denser than N7 which is what TSMC has said. Scott Jones is pretty sure M2P is ~ 30nm and 50nm for CPP which is what is needed to get the 1.8x density improvement they have discussed.

  2. As far as I understand it N5P is the same design rules, just more strain, a performance enhancement. Apple requires a new process every year so this is it. N5P will be out in 2021 for the Apple iProduct refresh. I would expect more optimizations will be announced next year so you may see a density improvement based on better EUV or something like that.
N6 was discussed, still on track for 2020 production. This will be the dominant node moving forward in my opinion, replacing N7 and N7+.
  1. N3 was not discussed but from what I understand it is FinFET based, N2 will be GAA. Samsung

  2. The TSMC process schedule is synced with Apple so N5 in 2020, N5P 2021, and N3 2022, absolutely.
It is interesting to note that TSMC made the claim that N7+ is the "first commercially available EUV process". Samsung announced commercialization of 7LPP in Q4 2018. Samsung announced 3nm is GAA earlier this year. It will be interesting to see who gets GAA into "commercial production first.

Anybody else?
Thanks Daniel. I appreciate you asking those questions. Scotten Jones was spot on with his calculations. Great work by Scotten.

 
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