The viability of fast following

[nghanayem]

Seems practical to me. If the "fast follower" provides MPW shuttles and good packaging options, I am sure they will do quite well.

This thought experiment was more so for a pure IDM. Foundries trying to be fast followers would have to convince people to migrate their designs to their late node. In the hypothetical example of this fast follower being two years behind, they might be one year behind on yields and 1.5-2 years behind on equipment depreciation. For a pureplay or primary foundry company this seems like a great way to end up with no wafer starts. For a pure IDM they would have a captive client that will wait for their node, and give them guaranteed wafer starts (assuming the higher costs per yielded mm^2 for fabless or fablite competitors prevent them from eating the IDM's lunch when they have a superior node). Put another way would the IDM be able to compete on price or with a larger die to make up for the density and performance benefits a newer less mature node that a fabless/lite competitor might use? Or even if executed properly would this fast follower IDM eventually be forced to go down either the path of AMD/IBM or that of Intel/Samsung?

I don't understand "lack of portability". Do you expect push button migrations? Is that what Intel does? For the RTL, don't they resynthesize, P&R, and adjust timing?

For analog, if the circuit designer saves their testbenches and takes good notes, etc, what is problem sliding over? The design is going to change anyway, because designs improve. More testability, calibration, etc. What was minimum before goes to the new minimum. Things not at minimum will probably get retuned. Use the same testbenches. The problem with migrations is typically due to not packaging up the design properly at the end of the project. The PM needs to be tarred and feathered.

Please explain what make the move so scary. 40 => 28... maybe not worth it. 40=>16... may be worth it.

It was at least my understanding that before 28nm UMC and TSMC nodes were literally plug and play. With the issues of gate first vs last, multi patterning, and finFETs ensuring that this could never be the case again.

 

[cliff]

UMC and TSMC... could be. I guess you can do that as a second source, but I would think that the next iteration of designs would typically be improved. I have never heard of a design going out the door on time without a mad scramble at the end, and features that didn't get pulled of the table. Engineers like feature creep.

 

[Paul2]

Please explain what make the move so scary. 40 => 28... maybe not worth it. 40=>16... may be worth it.

On 40+ you have not just 2 alternative fabs, but at least 4 fabs sharing processes close enough for push-button migration in between them all. That's the critical difference.

A lot of cheapest MCUs, and ASICs makers feel very comfortable on legacy nodes thanks to prices on older 300mm nodes being very even industry-wide, and peace of mind from that they can switch a fab easily.