Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/surecore-powermiser%E2%84%A2-low-power-sram-ip-now-on-samsung-28nm-fds-process-technology.12079/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

sureCore PowerMiser™ Low Power SRAM IP Now on Samsung 28nm FDS Process Technology

Daniel Nenni

Admin
Staff member
October 16, 2019/ Paul Wells / All, News

sureCore Limited, a provider of low power SRAM products and custom memory design services, today announced that its PowerMiserTM low power SRAM IP is now available for designs targeting the Samsung 28nm FDS process.

“As the low-power IC design and SRAM IP standard products leader, we’re responding to more and more enquires about the low-power consumption capabilities of silicon-on-insulator technology,” explained Paul Wells, sureCore CEO. “Making PowerMiser available on Samsung’s 28nm FDS technology responds to demands for low power devices, particularly those powering IoT, wearable, and medical applications.”
At the 28FDS process node, the single port PowerMiser supports a wide operating voltage range from 0.7V to 1.2V and demonstrates 50% dynamic and 20% leakage power savings of competitive offerings, depending on operating conditions. On-chip BIST and Byte Write capability, a key requirement for many embedded microcontroller designs, are also provided.

The compiler utilises sureCore’s patented, innovative microarchitecture techniques supporting single instance capacities to 576Kbit with word lengths of up to 144bits with three mux factors; 4, 8 and 16. It allows designers to trade-off between various memory sizes in terms of mux factor, depth, word length and local bit line length. It automatically generates datasheets, simulation model (Verilog), layout (LEF) and timing/power (Liberty) models to enable standard EDA tool flows.

The patented PowerMiser “Bit Line Voltage Control” technique virtually eliminates performance compromises at low operating voltages. Retentive sleep modes, including light sleep for rapid wake-up as well as deep-sleep for maximal leakage current savings, are also featured.

“sureCore providing PowerMiser for the Samsung 28FDS technology node creates competitive advantages to companies looking to manufacture low power, low leakage SoC designs. Adding a multi-dimensional low-power design resource such as sureCore is a real benefit for Samsung customers who are leading the way in delivering power efficient solutions,” said Kevin Yee, Director of IP & Ecosystem Marketing, Samsung Foundry.

FOR MORE INFORMATION CONTACT
Chuck Byers
chuck.byers@sure-core.com
 
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