[content] => 
    [params] => Array
            [0] => /forum/index.php?threads/struggling-to-reduce-vcc-min-on-sram%E2%80%99s.11561/

    [addOns] => Array
            [DL6/MLTP] => 13
            [Hampel/JobRunner] => 2000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000670
            [ThemeHouse/XPress] => 1010394
            [XF] => 2020170
            [XFI] => 1040070

    [wordpress] => /var/www/html

Struggling to reduce VCC-min on SRAM’s?

Daniel Nenni

Staff member
Reducing VCC-min in SRAM’s

SRAM Optimization Saves Power on SOC’s and Systems
Mobile device designers face the dilemma of reducing power and at the same time maintaining or increasing performance. Consumers will not tolerate increased battery life at the expense of performance. If it were otherwise, designers could simply dial back clock rates. Without this simple cure, the best way to reduce power for longer device operating life is to reduce supply voltage. While this is highly effective, it comes at a price.

The choke point for voltage reduction is usually SRAM. Decreases in supply voltage have an exponential effect on memory error rates. Upsizing bit cell transistors or switching to 8T or 10T configurations can alleviate this, but these approaches will increase area and possibly lead to increased leakage losses in all operating modes.
Once the bit cells are optimized as much as possible, the remaining factor is the efficiency of the power distribution network (PDN). If PDN losses can be minimized this acts as an effective reduction of vcc-min for the entire chip. Improvement in the PDN voltage drop at the worst endpoint will help the entire chip power performance.

Magwel’s resistance network solver, RNi™, is aimed directly at this kind of problem. It reads in the design GDS containing the full PDN. Users can select or define equipotential contacts anywhere on the network. Using information easily obtained from the foundry supplied ITF file for back-end metallization resistivities, RNi™ meshes and then rapidly solves the entire PDN. When it is finished, not only are the endpoint resistances available, but so are the point-to-point (p2p) resistances at all points along the net back to the specified contacts or top-level pads.

To make it as easy as possible to interpret the results, RNi™ displays the resistance values in its Field View, showing colors to indicated resistance. Mousing over any metal will reveal the numeric resistance value to that point. Usually a designer will set the contacts to be the top-level pads for the net of interest. However, RNi™ has the flexibility to solve for resistances from any arbitrary point in the network. Users can easily create a contact /pad anywhere they choose.

Recently a large Taiwanese memory chip company, made a breakthrough in power efficiency with RNi™. Using RNi™ they were able to reduce the voltage drop by nearly 100mv in their SRAM PDN. Let’s look closer at how RNi™ was helpful in reducing the PDN resistance in critical locations. The main technique consists of visual examination using the Field View in RNi™ to locate endpoints on the first metal layer that are over 10 ohms. This can be done by setting the color scale so that 10 ohms, for instance, is red. Because memory chips only use few metal layers and there is a fixed pitch, when a resistive end point is found it is usually easiest to add parallel wires to the PDN to reduce resistance and carry more current.

Connection by Abutment Leaves Gap.

Notice the sharp color change due to non-connection at abutment point

RNi™ is especially useful for locating design errors that can contribute to higher than necessary end-point resistance. One of these is gaps in abutment connections. These gaps are hard to see and can go unnoticed. In the RNi™ Field View they are easy to identify because of an abrupt color change along a wire. The resistances, and display color, along the broken connection do not change monotonically, but rather have a sharp change that is readily visible.

Missing Connections Create Large Voltage Drops on PDN’s. Note the red horizontal nets on the left side, as their resistance goes up

Missing Connections Create Large Voltage Drops on PDN’s

Note the red horizontal nets on the left side, as their resistance goes up

The other usually hard to find problem is missing vias. A missing via can escape detection because other parallel connections provide continuity; but they can have a major impact on PDN resistance. In RNi™, the Field View will show a sharp contrast in the colors of the crossing wires.

Resistance extraction tools can help identify which endpoint has the highest interconnect resistance. However, PDN’s have unusual topologies with large size, many self-intersections, and wide and thick metals, metal slotting and parallel paths. All of these traits make it harder to efficiently and accurately extract metal resistance. This difficulty only grows when it is important to identify the specific sections of the PDN’s that are contributing most to endpoint voltage drop.

Alternatively, there are 2.5 and 3D field solvers that can precisely extract resistance. The downsides of these solvers are that they are difficult to set up, run slow, and often only output a lumped resistive netlist. Instead what is needed is a tool that requires no specialized training and does not convert the PDN into a lumped netlist.
There is now an effective tool for locating portions of PDN’s with higher voltage drop. Every millivolt saved on the PDN translates into lower operating voltage and significant power savings without compromising performance.

More information on RNi™