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Storage And Computing Integrated Chip, Possibly Going From End To Cloud In The Next Few Years
As the computing power increases, number of processor cores are increasing, while available bandwidth per core is decreasing, which limits the overall speed. Transportation of data has become a considerable bottleneck. At the same time, energy consumption has also become a problem. Energy consumption of transferring data from external memory and on-chip storage is huge; and data transfer time is hundreds of times the computing time, and even thousands of times.
In the era of AI development, the storage barrier problem has increasingly become a bottleneck for the continuous improvement of computing power. Therefore, the industry has proposed a non-von Neumann architecture, which combines the traditional and computing-centric von Neumann architecture, changing the computing paradigm, and pushing part of the computing power down to storage, that is also the discussion about in-memory computing.
There are different implementations of this concept. Usually, this storage-computation integrated structure can be understood as embedding algorithms in the memory, and the storage unit itself has computing power, which theoretically eliminates the delay and power consumption of data access. This chip is especially suitable for neural networks.
Recently on the "chip" roadshow of the Semiconductor Industry Development Summit Forum in the Second China (Shanghai) Free Trade Zone Lingang New Area, Beijing Zhicun Technology Co., Ltd. CEO Wang Shaodi talked about his own WTM2101: an integrated chip for storage and computing; and Zhicun’s strategic plan for the future.
Solution to the Memory Barrier Problem
The following picture given by Wang Shaodi mentions some typical data about the storage barrier problem; it mainly reflects that with the advancement of process technology, the computing power of the processor is getting stronger and faster, the calculation speed is getting faster and faster, and the storage capacity is increasing, but the memory bandwidth is difficult to achieve on year-on-year growth.
As the computing power increases, the number of processor cores increases, and the available bandwidth per core decreases, which limits the overall speed. "Transportation of data has become a considerable bottleneck." "At the same time, energy consumption is also a problem." The energy consumption of transferring data from external memory and on-chip storage is huge; and "data transfer time is hundreds of times the computing time, even thousands of times."
"This is why the storage and computation integrated solution is required. The most fundamental solution to the storage wall is to integrate storage and computation together, and use storage units to do computation." Wang Shaodi said.
"The name of in-memory computation may sound better. It is to use memory to do computation. The whole is a computation type chip. The computation medium is memory, not a logical operation unit." The above picture compares the structural differences between the two. The circle represents the storage unit.
It is different from the traditional computing architecture storage subsystem that activates one row at a time and completes data reading in sequence; the storage-computing integrated architecture activates multiple rows and multiple columns at the same time. "The horizontal axis is no longer a selection signal, but actually the data being processed." The process needs to be converted to an analog circuit-previously we also mentioned that the Ohm's law of a single device is used to complete a multiplication, and then Kirchhoff's law is used to complete the column. In this way, the storage device unit is used to complete the multiply-add calculation.
"One memory operation cycle can complete 1 million parameter multiplication and addition operations, and the efficiency is increased by 50-100 times." Obviously, this is quite valuable for AI.
In terms of more specific usage scenarios, for AI computing from the end side to the cloud, flexible expansion of computing power seems to have a natural advantage in chip products that integrate storage and computing. "The computing power of 2MB, 4MB, and 8MB memory is relatively low and can be used by end-side devices; the storage and computing integrated array can reach 128MB, and it can be used for the edge side; storage capacity reaches 1GB, 2GB, 4GB, and it can provide more than 1000TOPS computing power by using the cloud scene."
"It will take 5-8 years for the storage and computation integration to cover AI computing scenarios, starting from the end side and the edge side." Wang Shaodi said. The above picture also clearly shows the AI chips in different scenarios, the future market size and its development potential-these should also be well-known.
From Zhicun 1.0 to Zhicun 3.0
Viewing from the company's development path, the two founders have relatively early experience in participating in the research and development of the US' storage and computing integration project; in 2017, Zhicun Technology was established, and it received an angel round of financing the following year. This is still a very young company. In 2019, Zhicun cooperated with internationally renowned companies to develop integrated IP storage and computing, and completed the tapeout of IP and SoC test chips, and released the first integrated storage and computing chip in the world.
In 2020, Zhicun has completed the world's first storage-computing integrated chip mass production and commissioning and the world's first storage-computing integrated SoC chip verification. The WTM2101 storage-computing integrated chip introduced by Wang Shaodi is expected to be mass-produced in the fourth quarter of this year. It seems that the development of the concept of storage and computation in one is much faster than we expected.
The left side of the above picture is the WTM2101 chip architecture diagram. The main part of the memory with storage and computation is that "most of the operations are completed by the integration of storage and computation." In addition, it is also equipped with a RISC-V CPU to provide non-matrix computation.
"Compared with the computing power and power consumption of the existing market solutions, WTM2101 has an advantage of more than 10 times." Although it is not clear what the "market existing solutions" in this figure is, the algorithm complexity in the column of WTM2101 and power consumption are indeed quite amazing.
In addition to introducing products, Wang Shaodi also talked about Zhicun's strategic planning. From the establishment of the company to 2020 is the "Era of Zhicun 1.0". At this stage, "Developing storage and computing integrated technology and applying it to voice scenarios", Wang Shaodi also emphasized once again that "We are the first company in the world to implement technology."
From this year to 2024 is the Zhicun 2.0 planning period, "further advance, advancing to 128MB, achieving 64-100TOPS computing power level, covering end-side and edge-side scenarios. We will choose advantageous scenarios to implement applications."
After 2024, the chip will "push to the cloud", with a capacity of 1GB to achieve the computing power range of 500-2000TOPS, and the product will achieve vehicle-level reliability. "After 2025, we plan to launch standardized products. After that, the products will no longer be oriented to application scenarios, but will provide different capacities like memory, integrate with existing computing systems, and complete such integration with advanced packaging technology. At the same time, we have also launched a corresponding tool chain, which is fully adapted to the integration of storage and computing technology to adapt to mainstream artificial intelligence algorithms."
Note that the revenue on the horizontal axis and the market value expectations on the vertical axis of this chart indicate that this company has sufficient confidence in the short-term future development. Perhaps this picture itself can also represent the development trend of the storage-computing integrated technology in the next few years.