Event Details
Radisson Blu Bengaluru, Bangalore
Sept 25 - 26, 2019
Booth #4
Synopsys-featured Tutorials
Sept 25, 2:00 p.m. - 3:30 p.m. | Grand Victoria A
Simulation Acceleration to Speed Block and Platform Level IP Verification
Simulation Acceleration effectively addresses the runtime performance challenges of a simulation platform, by providing up to 100X speedup over simulation. This enables users to not only find bugs quicker, but also achieve a “shift left” through performance analysis and power estimation much earlier in the design cycle.
This tutorial discusses the new simulation acceleration technology with the Synopsys VCS functional verification solution and ZeBu emulation system.
Sept 25, 4:00 p.m. - 5:30 p.m. | Robusta
Using the Synopsys Verification Continuum Platform to Speed PCIe System Verification
PCIe as a high speed and high throughput bus is used more and more frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels. In this tutorial, we will introduce 3 typical solutions: PCIe verification IP for System/PCS/SERDES verification, virtual host PCIe solution with ZeBu emulator, and prototyping solution for system validation with HAPS, that enable chip designers to meet the power, performance and area requirements and “shift-left” PCIe verification.
Sept 25, 9:45 a.m. - 10:30 a.m. | Grand Victoria Ballroom
Join Sridhar Seshadri, VP of R&D in the Verification Group, for the Synopsys Keynote.
This presentation looks at the static verification landscape and how it has evolved to support chip complexity, along with the unique challenges and opportunities posed by sophisticated chips for automotive systems, AR/VR platforms, and AI applications with 5G connectivity.
You can also see Synopsys at the AL/ML in Design & Verification panel on Sept 25, 12:20 p.m. -1:00 p.m. in the Grand Victoria Ballroom.
And learn more about the Synopsys Verification Continuum Platform in booth #4!
Radisson Blu Bengaluru, Bangalore
Sept 25 - 26, 2019
Booth #4
Synopsys-featured Tutorials
Sept 25, 2:00 p.m. - 3:30 p.m. | Grand Victoria A
Simulation Acceleration to Speed Block and Platform Level IP Verification
Simulation Acceleration effectively addresses the runtime performance challenges of a simulation platform, by providing up to 100X speedup over simulation. This enables users to not only find bugs quicker, but also achieve a “shift left” through performance analysis and power estimation much earlier in the design cycle.
This tutorial discusses the new simulation acceleration technology with the Synopsys VCS functional verification solution and ZeBu emulation system.
Sept 25, 4:00 p.m. - 5:30 p.m. | Robusta
Using the Synopsys Verification Continuum Platform to Speed PCIe System Verification
PCIe as a high speed and high throughput bus is used more and more frequently, especially for high-performance computing, AI, and 5G applications. PCIe verification is complex as requirements stem from many levels. In this tutorial, we will introduce 3 typical solutions: PCIe verification IP for System/PCS/SERDES verification, virtual host PCIe solution with ZeBu emulator, and prototyping solution for system validation with HAPS, that enable chip designers to meet the power, performance and area requirements and “shift-left” PCIe verification.
Keynote: The Evolution of Static VerificationSept 25, 9:45 a.m. - 10:30 a.m. | Grand Victoria Ballroom
Join Sridhar Seshadri, VP of R&D in the Verification Group, for the Synopsys Keynote.
This presentation looks at the static verification landscape and how it has evolved to support chip complexity, along with the unique challenges and opportunities posed by sophisticated chips for automotive systems, AR/VR platforms, and AI applications with 5G connectivity.
You can also see Synopsys at the AL/ML in Design & Verification panel on Sept 25, 12:20 p.m. -1:00 p.m. in the Grand Victoria Ballroom.
And learn more about the Synopsys Verification Continuum Platform in booth #4!