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Reduce the latency of your arm-based CXL multichip interconnect with CXS-B

Daniel Nenni

Staff member
PLDA’s industry-leading XpressLINK-SOC™ CXL IP provides full support for the AMBA® CXS Issue B (CXS-B) interface protocol. This support enables SoC designers to reduce latency and more easily implement the CXL and CCIX multichip interconnect standards in their Arm®-based System-on Chip (SoC) solutions.

AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller. Using a CXS interface, the designer can bypass the controller’s transaction layer, which can significantly reduce latency. The CXS specification defines the interface between an on-chip interconnect, such as the Arm CoreLink™ Coherent Mesh Network, and a PCIe or CXL controller to optimize transport of CCIX and CXL packets.

XpressLINK-SOC Controller IP for CXL supports:
  • The AMBA AXI Protocol Specification for traffic
  • Either the Intel CXL-cache/mem Protocol Interface (CPI), the AMBA CXS-B Interface or the AMBA AXI Protocol Specification for CXL.mem
  • Either a CPI interface or the AMBA CXS-B Protocol Specification for CXL.cache traffic.

Please feel free to contact us if you have any questions or have an active project that you would like to discuss.

Best regards,