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Yes, Apple will be the first to TSMC 7nm, we should see new iPads in Q2 2018. The problem with iPads is that they last too long. I had my iPad 2 for 4+ years before replacing it with an iPad Pro and I couldn't be happier with the performance.
It should also be known that Apple uses a custom version of 7nm that others do not use. So comparing TSMC Symposium PowerPoint slides to the process Apple uses is not an apples to apples comparison.... See what I did there?
Thanks for the clarification. btw TSMC hitting HVM ramp in Q1 2018 sounds very achievable since they have been in risk production from Apr 2017 and recently TSMC said in their Q3 earnings call that they have moved 7nm from R&D to manufacturing which I assume means moving 7nm from risk to the start of high volume production.
http://www.tsmc.com/uploadfile/ir/quarterly/2017/3FBfm/E/TSMC 3Q17 transcript.pdf
"Now, let me move to N7 and N7+. N7 been transferred from R&D to manufacturing in early third quarter this year. Right now, our efforts focus on defect reduction and fine-tuning device performance to prepare for mass production in the first half of 2018.We expect the yield learning in N7 to benefit greatly from N10 and our progress so far has been on schedule. The initial application for N7are high-end application processors and high-performance computing. We are working with major customers for their products to be introduced in 2018. We expect more than 50 tape-outs by the end of 2018"
Since Apple is looking at A11x for 2018 iPad to be manufactured at 7nm and ship by mid-2018 , I think the TSMC N7 HVM ramp is well underway and we will see production chips start to ship to Apple supply chain by the end of Q1 2018 or early-mid Q2 2018. On the topic of GF 7nm they are still yet to start risk production and have stated risk production before mid-2018, which I assume means Q2 2018. I have my doubts as to whether GF 7nm HVM ramp can happen even by late 2018. imo I think GF 7LP HVM ramp is more a Q1 2019 event and I think TSMC has a solid 1 year time to market lead over GF 7nm. As for Intel well I am hearing the worst rumours and that their 10nm could slip into 2019 and that Cannonlake might be produced in very small volume in H2 2018 or be totally scrapped. Icelake on 10+ in H1 2019 seems to be the first real high volume product from Intel on 10nm process. I would like to hear your thoughts on when GF could ramp 7LP to HVM and what you are hearing on Intel 10nm too.
Yes, I believe it is the Snapdragon 855. Here is the backstory in case you are interested:
QCOM and TSMC were best friends until Apple came to TSMC at 20nm. With Apple as TSMC's best friend QCOM went to Samsung at 14nm. Samsung 14nm was very good so QCOM stayed for 10nm. Samsung 10nm was a catastrophe, it did not yield so QCOM jumped over to TSMC 7nm. That is QCOM in a nutshell by the way.
I'm really interested to see a benchmark between the 10nm an 7nm Snapdragons. The should be close to an apples-to-apples process comparison.
Yes, I believe it is the Snapdragon 855. Here is the backstory in case you are interested:
QCOM and TSMC were best friends until Apple came to TSMC at 20nm. With Apple as TSMC's best friend QCOM went to Samsung at 14nm. Samsung 14nm was very good so QCOM stayed for 10nm. Samsung 10nm was a catastrophe, it did not yield so QCOM jumped over to TSMC 7nm. That is QCOM in a nutshell by the way.
I'm really interested to see a benchmark between the 10nm an 7nm Snapdragons. The should be close to an apples-to-apples process comparison.
The yield problems were only at the beginning. It would have been the same situation or worse if they had stayed with TSMC at 10nm. And they would have lost the opportunity to be used in Samsung's S8 family in the first half of 2017.
Can TSMC really ramp in to volume production 2 products in a node that just went to mass production ? Qualcomm+Apple ( maybe Huawei too ) in the second half of this year ?
The reason Qualcomm switched to Samsung was to not wait for Apple to get leading edge nodes.
The yield problems were only at the beginning. It would have been the same situation or worse if they had stayed with TSMC at 10nm. And they would have lost the opportunity to be used in Samsung's S8 family in the first half of 2017.
Can TSMC really ramp in to volume production 2 products in a node that just went to mass production ? Qualcomm+Apple ( maybe Huawei too ) in the second half of this year ?
The reason Qualcomm switched to Samsung was to not wait for Apple to get leading edge nodes.
I think Apple will get production 7nm in Q1 2018 and the rest (QCOM, Mediatech, Huawei, etc...) in Q2. Remember, 7nm uses the same fabs as 10nm so significant yield learning has been achieved. And after 7nm comes 7nm+ (EUV) in 2019 (same fabs) which I am told is already doing quite well. I will be in Hsinchu later this month and will know more then.
Apple did get preferential treatment by TSMC, something like "most favored nation" status which included wafer availability and pricing. And remember, Apple gets an exclusive version of the process. But if you look at TSMC financials since 20nm when Apple came to Hsinchu TSMC margins have never been better and TSM stock price has about doubled so job well done in getting Apple to play and stay at TSMC.
It would be more unusual if Apple used exactly the same 7nm process as others, than it is for them to have their own spin.
When you are the yield learning vehicle in a node, as Apple clearly is, you are at somewhat of a disadvantage compared to the fast followers. It seems like the pure foundry model works best for the fast followers who the leader enables. I think the real victory for a foundry, is when you have both: A pipecleaner product which establishes the node, and some followers who increase the volume and make the node sustainable.
With the narrowing of the customer base at advanced nodes, you are starting to see 1-2 customer nodes, almost like an IDM. If the trend continues, we'll start to see the dissolving of the foundry model into a sort of IDM-for-hire model.
It would be more unusual if Apple used exactly the same 7nm process as others, than it is for them to have their own spin.
When you are the yield learning vehicle in a node, as Apple clearly is, you are at somewhat of a disadvantage compared to the fast followers. It seems like the pure foundry model works best for the fast followers who the leader enables. I think the real victory for a foundry, is when you have both: A pipe cleaner product which establishes the node, and some followers who increase the volume and make the node sustainable.
With the narrowing of the customer base at advanced nodes, you are starting to see 1-2 customer nodes, almost like an IDM. If the trend continues, we'll start to see the dissolving of the foundry model into a sort of IDM-for-hire model.
That's not really how it works. As a fabless company you want to be part of the process development and ramping so you get both first input into the specs and first output of wafers. Yes it is more expensive but the extra cost is nothing for companies like Apple and Nvidia. It didn't used to work that way of course. FPGA companies (Altera/Xilinx) were the pipecleaners. Then came the SoC revolution with QCOM and Mediatek and of course Apple now trumps them all. With the AI surge Nvidia also ranks right up there and will get a custom HP process at 7nm.
The foundry model has definitely evolved with Apple driving TSMC and AMD driving GF but it is still a fabless semiconductor model. If not for Apple and AMD would TSMC and GF be ahead of Intel? Not in my opinion. And then there is the fabless semiconductor ecosystem which is a force of nature and will continue to dominate the semiconductor industry, absolutely.
Dan the foundry model has a killer app; choice. The network effects of a common, openly licensed architecture (ARM) are also obvious. So choice and network effects are both very powerful.
Vertical integration seems to be growing though. Qualcomm is in the process of buying NXP which is a fab operator. I think China and choice do not mix and I am skeptical that foundries will truly have the same business model there. And as we approach maturity in semiconductors, the drive to reduce costs and remove a middle man (the foundry) will only grow greater and greater. I wouldn't assume the rear-view mirror (which is really just a story of one foundry success) will apply in the future.
After Qualcomm gave the Snapdragon 855 volume to TSMC for the Galaxy S10 (due in 2019), it looks very unlikely to me that they will switch back to Samsung for the Galaxy S11 (due in 2020) as that would require Samsung's EUV-heavy "7nm" or "6nm" process to be on time. Even with their strong ties, it looks very unlikely given unresolved availability concerns with higher power EUV.
In summary, TSMC looks likely to take the lion's share at 7nm and even GF could have larger 7nm foundry share than Samsung in the next few years. Samsung's heavy bet on EUV (10+ layers etc) appears to have not paid off at all - a more measured, dual-track approach would have been the better strategy, but they were so late, they tried to take a big risk. At least, they can try and use the tools already ordered for DRAM in the short-term.
As usual I mostly agree with Daniel, but when talking Samsung please always consider that it is essentially a huge memory maker with a very large fabless and a mid size foundry. If they can have outside foundry customers partially paying for EUV introduction in their fabs, that will help in achieving even bigger gains from the memory business where EUV litho impact on costs and performance can be even larger than in logic (and Toshiba, Micron and Hynix will have more problems than TSMC following). So the choice of pushing an earlier EUV introduction is less damaging than it looks like, in my opinion.
Samsung is moving to mid-teen (1y) nm DRAM to keep ahead of the others, without EUV. That also happens to be about where the EUV tools lose their practical resolution.
Samsung is moving to mid-teen (1y) nm DRAM to keep ahead of the others, without EUV. That also happens to be about where the EUV tools lose their practical resolution.
Attention, the naming game is true also in DRAM, in 1y there is nothing at 10nm, no more than there is anything that is 7nm in TSMC/Intel/Samsung. And there is also the market of 3D NAND (today stuck at 40-60nm pitches). In both the pitch and image fidelity (i.e. process window) would still benefit from EUV if it becomes suitable for production.
And ASML/Zeiss have started looking into 0.55 NA for EUV that would extend the resolution.
Attention, the naming game is true also in DRAM, in 1y there is nothing at 10nm, no more than there is anything that is 7nm in TSMC/Intel/Samsung. And there is also the market of 3D NAND (today stuck at 40-60nm pitches). In both the pitch and image fidelity (i.e. process window) would still benefit from EUV if it becomes suitable for production.
And ASML/Zeiss have started looking into 0.55 NA for EUV that would extend the resolution.
The DRAM cell dimensions are not so easy to escape scrutiny. TechInsights regularly reverse engineers leading edge products. Samsung previously showed 18 nm half-pitch in the active silicon cell area. Micron and SK Hynix are following closely, so I would guess Samsung 1y is about 16 nm. The NXE:3400 tool feature details were disclosed last year, it is not good at direct exposure at this resolution, showing in tip gap difficulties. So SAQP cannot be avoided. But the other concern is the finer cutting still requires higher EUV doses, due to photon shot noise. 1y shouldn't require extra cutting compared to 18 nm on currently used tools.
I see your point Fred, but assuming EUV is up for real production wouldn't you prefer double EUV exposure to quadruple exposure with immersion? Even if in memory mask cost is negligible, the reduction in number of process steps can still be important. I am also interested in your opinion of EUV impact in NAND.
(confession to make, I am not very good at DRAM ...)
I see your point Fred, but assuming EUV is up for real production wouldn't you prefer double EUV exposure to quadruple exposure with immersion? Even if in memory mask cost is negligible, the reduction in number of process steps can still be important. I am also interested in your opinion of EUV impact in NAND.
(confession to make, I am not very good at DRAM ...)
Comparing the number of process steps (EUV vs immersion) seems to assume comparable throughputs. But actually you can have something like 4000 wafers/day immersion vs. 1000 wafers/day EUV (the EUV throughput depends on dose). So if you had 4 days for 4 passes, after 4 days 4000 wafers completed the layer with immersion quadruple patterning, while 2000 (1000+1000) wafers completed the layer with EUV double patterning. In memory, Samsung and others are using numerous ways to keep the number of masks to a minimum. It's a little easier because all the features are on a grid. For 3D NAND, they have stopped shrinking but actually still use double patterning, which we can imagine or surmise is still faster than EUV.
Comparing the number of process steps (EUV vs immersion) seems to assume comparable throughputs. But actually you can have something like 4000 wafers/day immersion vs. 1000 wafers/day EUV (the EUV throughput depends on dose).
That is the reason I was saying "assuming EUV is up for real production". So let's say instead of one fourth, only one half of the throughput.
For NAND I see an interest, if one can shrink pitch again, of reducing the spacing vs augmenting the number of layers. Thanks for the useful debate.
Yes, I believe it is the Snapdragon 855. Here is the backstory in case you are interested:
QCOM and TSMC were best friends until Apple came to TSMC at 20nm. With Apple as TSMC's best friend QCOM went to Samsung at 14nm. Samsung 14nm was very good so QCOM stayed for 10nm. Samsung 10nm was a catastrophe, it did not yield so QCOM jumped over to TSMC 7nm. That is QCOM in a nutshell by the way.
QC's TSMC 20nm SoCs were the worst in the history of mobile semiconductors.
I love how you omit the fact that QC went for a second generation SS 10LPP even though it was so bad. And how was 10LPE a catastrophe while being 6 months ahead to mass production compared to TSMC while performing the same as the latter?
QC jumped to TSMC 7nm simply because for the release cycle of the 855 (Q1 2019) Samsung won't have 7nm volume production ready in time.
QC's TSMC 20nm SoCs were the worst in the history of mobile semiconductors.
I love how you omit the fact that QC went for a second generation SS 10LPP even though it was so bad. And how was 10LPE a catastrophe while being 6 months ahead to mass production compared to TSMC while performing the same as the latter?
QC jumped to TSMC 7nm simply because for the release cycle of the 855 (Q1 2019) Samsung won't have 7nm volume production ready in time.
Might as well benchmark a toaster against a microwave because those two generations won't have any common IP in-between them.
S855 on TSMC 7nm is a single time thing at the high-end. If we're lucky we might see a 855 vs 865 7vs7nm comparison, although again the IP will be different by then.
