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Problem to understand diffusion capacitance in PN junction and forward bias diode resistance

Eva713

New member
Hi, all
Recently, I have read some articles about PN junction, one of them (data source: Analysis in PN Junction Diode) impressed me deeply and had such doubts What is the concept behind diffusion capacitance and on resistance of the diode? Can we consider diffusion capacitance as a parallel plate capacitor ? It is easier to see the depletion capacitance and its calculation but diffusion capacitance calculation is very confusing ? Does the on resistance comes from carrier scattering?:unsure:

Is there anyone give me some ideas? Many thanks.
 

sntsh

New member
Hi Eva713, I had similar questions about diffusion capacitance a few years ago while working on modeling ESD diodes. I recommend checking out Taur and Ning's semiconductor book which has a good description about this.

Others can correct me if I am wrong. In short, the diffusion capacitance is present only when diode is forward biased. This pushes holes from p-side and electrons from n-side to opposite junctions where they start recombining with the oppositely charged majority carriers. But this recombination while take a little while to clear out all the charge being pushed in. During this time, there is a build up of this additional charge opposing charge on either side of the (now smaller) depletion region and gives rise to additional capacitance called diffusion capacitance. As forward bias increases, this diff cap goes up but only until the diode turns ON (i.e. the depletion region is too small/negligible and there is no longer any barrier for carrier injection).

The on-resistance of a diode (the linear I-V curve that you get when diode turns ON) is from any parasitic metal lines that are in series to the p-n diode. After diode turns ON, the diode itself has negligible resistance and we only see any remaining series resistance either from your contacts or metal lines.
 

Eric Esteve

Moderator
As far as I remember my PhD work (1985) done on parasitic capacitance measurement on CMOS 2 micron technology (!), any P-N junction built on source or drain of the transistor will create a parasitic capacitance.
We had to make measurement, then modeling, to feed the SPICE transistor model in order to run more accurate simulation.
Interesting was the fact that the theory give Cj = (xyz) Exp 1/2
and the measure the same function, but Exp 1/3 or 1/4
This was due to the small geometry (at that time) and configuration of the junction...
 

Eva713

New member
Thank you for sharing. 😊
I understand the concept for the resistance but I will rephrase my question for the diffusion capacitance. So diffusion capacitance comes into play in the forward bias because of the minority carriers in each of P and N region of the diode. As we change the forward bias across the PN junction, these minority carriers will change. Since the change in charge happening w.r.t. change in voltage and that results in capacitance.....which is Diffusion-..... Can we think of this Capacitance as Parallel plate Capacitor with a very thin Dielectric (since the Depletion region is very small) and the charge on the plates which is changing is minority carriers ?

For Depletion Capacitance- with the change in reverse voltage, depletion width is changing- charge in P and N region is changing which again is similar to Parallel plate capacitance . Am I right ?
 

lorenso

New member
What software for this task you can recommend at first? Custom software development by https://mlsdev.com/services/ui-ux-design methodologies include a series of software development methodologies. The software methodologies determine the software architecture. Next, the software development methodology determines the software design. Finally, the software is tested for its functionality and reliability according to the software testing methodology. When software testing is complete, software developers create the software using the test designs they created using the software testing methodology.
 
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