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Pre-Sales Customer Solutions Engineering - San Jose (ASIC/IP, Customer Facing)


New member
eSilicon, an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions, is seeking a highly regarded, customer-facing, semiconductor technologist to act as a primary technical resource providing comprehensive Technical Solutions to its Customers.

The position is based in San Jose, CA.

Responsibilities include:

  • Primary customer interface for all technical support activities during the Pre-Sales Process.
  • Represent eSilicon technical expertise in front of current and potential customers.
  • Work closely with eSilicon Sales, Marketing, and Technology groups to craft proposed solutions for Customers.
  • Align with IP suppliers to understand their products and benefits to eSilicon customers. Work with customers and IP suppliers to target best solutions.
  • Work with IP supplier on custom solutions or road map development as needed.
  • Analyze eSilicon solutions as they relate to competition.
  • Work closely with Marketing to adjust proposals or roadmaps as needed.
  • Develop technical presentations.
  • Understand and continue to develop our technical and commercial differentiation

Skillset must include

Excellent communication Skills:

  • Must have excellent written and presentation skills
  • Well regarded by colleagues as a self starter with superior ability to craft solutions to complex problems with little to no input.
  • Comfortable and experienced as leading technologist in customer-facing roles.

Very familiar with ASIC process technology including:

  • Different technology nodes and relevant features
  • Experience with multiple foundries, with emphasis on TSMC
  • Experience with advanced process nodes – 28/16/14/7nm
  • Experience in large, complex design
  • Key performance metrics
  • Fabrication process
  • Prototype bring up
  • Production Qualification process
  • Knowledge of FA a plus
  • Experienced in ASIC Physical design
    • Timing analysis using STA
    • Floorplanning
    • Place and Route
    • Clock tree architectural decisions and implementation
    • Timing closure
    • Timing Signoff Methodology
    • Low power techniques
  • Experienced in ASIC Design For Test (DFT)
  • Understanding of ASIC handoff processes
  • Knowledge in IP
    • Familiar with foundation IP (Standard cell libraries, IO, memory, PLL)
    • Familiar with common hard IP blocks (SerdDes, MXS, processors)
    • Familiar with common soft IP blocks (memory controllers, SerDes controllers.)
  • Package
    • Familiar with broad range of package technology
    • Can work with package engineering to select cost competitive solutions
    • Familiar with package and board level Signal Integrity analysis
Education and Experience to include:

  • BS EE Degree
  • Minimum 10 years experience in ASIC industry
Must be eligible to work in the US without restrictions.
Travel required. attention: S Marinucci

Check out all eSilicon openings