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Physical Design Engineers (SOC & AMS), Apple, Munich, Germany


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[FONT=&quot]Apple's R&D centre in Munich, Germany is seeking Physical Design Engineers (Both SoC & AMS) to develop future Processors in the EU.[/FONT]

[FONT=&quot]If you are located within the EU and want to explore these opportunities, then drop me a line.[/FONT]

[FONT=&quot]Job Summary[/FONT]
[FONT=&quot]Experience with Place & Route tools Synopsys or Cadence.[/FONT]
[FONT=&quot]Familiar with hierarchical design approach, top-down design, timing and physical convergence.[/FONT]
[FONT=&quot]In-depth understanding of STA, extensive know-how in clock/power distribution, analysis, as well as RC extraction and correlation.[/FONT]
[FONT=&quot]Experience with SoC practices, multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.[/FONT]
[FONT=&quot]Scripting and programming using several of the following: Perl, TCL and Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ beyond.[/FONT]
[FONT=&quot]Knowledge of Verilog.[/FONT]

[FONT=&quot]- Implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology[/FONT]
[FONT=&quot]- Own block level PnR, floor-planning, clock & power distribution[/FONT]
[FONT=&quot]- Do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS)[/FONT]
[FONT=&quot]- Developing/validating high performance low power clock network guidelines[/FONT]
[FONT=&quot]Education BSEE, MSEE[/FONT]