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Physical Design Engineers @ Apple, Munich, Germany

nickatapple

New member
With the A13 Bionic chip announcement of our fastest CPU & GPU in a smartphone, we are continuing to advance the technology, power & performance even further.

With our rapid growth in Europe, we are seeking Physical Design Engineers (SoC & AMS) to join our team here in Munich, Germany. If you are located within Europe and want to explore these opportunities, then please reach out to me.

Danke!
Nick
#apple #futureofsilicon #munich #münchen

Job Summary
Experience with Place & Route tools Synopsys or Cadence.
Familiar with hierarchical design approach, top-down design, timing & physical convergence.
In-depth understanding of STA, extensive know-how in clock/power distribution, analysis, RC extraction and correlation.
Experience with SoC practices, multiple voltage and clock domains, integration of mixed-signal IPs & I/O integration.
Scripting & programming using several of the following: Perl, TCL & experience with SoC designs (>20M gates) with frequencies in excess of 1GHZ beyond.
Knowledge of Verilog.

Description
- Implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology
- Own block level PnR, floor-planning, clock & power distribution
- Do power & noise analysis (EM / IR-Drop / Xtalk) + layout verification (DRC / LVS)
- Developing/validating high performance low power clock network guidelines
Education BSEE, MSEEm
 
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