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New to Riviera-PRO™: VHDL-2019 Support and a Versatile UVM Registers Window

Daniel Nenni

Admin
Staff member
Henderson, NV – June 24, 2020Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added VHDL-2019 feature support and a UVM Registers window to Riviera-PRO™, the company’s popular, high performance simulation and debugging tool.

The VHDL-2019 features supported are: Interfaces; Conditional Compilation; Shared Variables on Entity Interfaces; API for Assert (without PSL); API for Calling Path Information (in debug mode); Conditional Expression; and API to access Date, Time and File System.
“Since the ratification of VHDL-2019 as IEEE Std 1076-2019, we’ve been keen to give our users access to as many of the language’s new features as possible,” comments Sunil Sahoo, SW Product Manager.

As for the UVM Registers window, it lists UVM RAL register models and their properties. Register models can be viewed as a hierarchy of register blocks or as a memory map. The contents of registers and their fields from the UVM model, plus the HDL implementation, are visualized in this window, which can be exported as CSV files for use as input data for the register generator.

The new release of Riviera-PRO also has updated UVVM libraries – updated to the 2020 03 03b version of the open-source and increasingly popular Universal VHDL Verification Methodology.

Sahoo concludes: “It is essential for all EDA tools to keep up to date with not only the industry’s most popular languages but also those verification methodologies that stand to really boost productivity.”

Riviera-PRO 2020.04 is now available for download and evaluation.
 
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