Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/near-threshold-voltage-ntv-panel-part-3-of-3.13742/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020570
            [XFI] => 1050070
        )

    [wordpress] => /var/www/html
)

Near Threshold Voltage (NTV) Panel - Part 3 of 3

Daniel Nenni

Admin
Staff member
Experts around the world helped to educate us during the 2020 Virtual 57th Design Automation Conference (DAC) on where NTV is headed, why it’s it not a free lunch and how the industry is working together to make it work for certain applications. This is part 3 of a 3-part summary of the lively video discussion that took place between Brian Bailey, Semiconductor Engineering; Lauri Koskinen, Minima Processor; Mike Eftimakis, Arm; Joachim Rodrigues, Xenergic; and Lluis Paris, TSMC. If you missed the previous articles, here's a link to part 1 and part 2.

Brian: Memory – are memories going to be able to keep up with the kind of applications designers want to use NTV for?

Joachim
: It depends on the application of course. We use bit cells from the foundries. There are some limitations. We have been investing in the design flow. We are considering all the parameters. Consider the temperature range for medical applications, we don’t have to consider worst case temperature parameters of -40 degrees. Memories are definitely one of the bottlenecks for NTV. But this is something we’re addressing.

Lluis: Yes, we agree memories are a bottleneck. That’s why we’re coming out with a new bit cell. For instance, at 22nm, we used to have one generic leakage bit cell. We added ultra-low leakage bit cell. We’re adding another bit cell with thick oxide called extreme low leakage. The trade-off is that the very low leakage memory is very slow. Our customers for instance if they do microcontrollers, they may be used in medical, but they may be used in automotive. They need the support from -40 degrees to +150 degrees with the same bit cell. So, it means we have to make compromises. We need multiple different compilers. That’s where the work is. We need different bit cells options. Let customers decide. Some customers will go for cost and use one option. Some will go for flexibility and may use 2 or 3. One single solution that covers all the range doesn’t seem to be physically possible.

Lauri: Will we ever see an 8T bit cell for NTV?

Lluis
: We have 8T, 10T, 11T, 13T. Customers don’t like them, they take too much area. We have experiments, we have results. We like them a lot. Customers don’t like them. At the end of the day, customers decide. But they do exist.

Joachim: Customers are price sensitive. It’s too expensive in area. That’s why we’re making the 6T bit cell work for NTV. I should mention what adds complexity - relying on dual rail technology, meaning we need dual power suppliers. It’s not good enough to focus only on one point. Energy efficiency is from a system perspective, so as soon as we do voltage conversion its expensive in terms of energy. So, a single rail technology is something we’re promoting quite a lot.

If you are going for NTV, you have to have a vertical view on the design flow from the software down to the process. You have to consider all the different optimization possibilities. This is how you can make it work.

Lluis: There is a trade-off. If customer insists on 6T bit cell, then you have the noise margin. You’re limited by the threshold of the transistor. If you want a very low leakage bit cell and your threshold voltage is 0.7 volts, you can’t go single rail below 0.7 volts. You can read, you can write but you can’t do both. But that’s not very practical. If you want to solve that problem, you add transistors, but you pay in area. There is no free lunch. Customers decide what they want. Today they insist on 6 T That may have to change in the future because we all agree that’s a bottleneck. We offer dual rail to get around that. The other alternative is different bit cells.

Brian: Process variability, how big an issue are others finding this?

Lluis:
This is fundamental physics, when you get near to threshold, the variability is much bigger. Some sophisticated customers already know how to do it. In a normal process, the difference between a fast corner and slow corner is maybe 30%. That’s fine, you can close timing. But when you go to NTV, the difference is 20X so trying to close timing is impossible. What you need is adaptive voltage. You need to look at your silicon and if its slow, you raise the voltage. If it’s fast, you lower the voltage. You counter the variability. You need voltage regulation. You need very fine voltage regulation of 5-10 millivolts. There is no free lunch. Solutions exist and we try to show customers alternatives.

Brian: Wrapping up now, how does NTV play in with DVFS strategies?

Lauri
: You can’t do NTV without some kind of adaptivity. There are multiple ways to do it but you do end up with some other restrictions. It comes down to more intelligent solutions where you end up with better energy. I personally think they are very doable. We will see small chips where these solutions are still very cost effective.

Joachim: You need some adaptivity to work with many circuits. It depends on the application.

Mike: NTV is not the solution to all problems. You have to insert NTV into a variety of techniques to make your solution low power. I talk about solution and not just chip, it’s really a question of how you manage your chip, manage your software, and even how you write your software. It’s a lot of decision points and NTV is one additional tool in this toolbox.

Part 1
Part 2
 
Top