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Minimum number of M2 tracks over a standard cell

nghanayem

Well-known member
With N5/3 having a 9 track HP cell and a 5 track HD cell, and intel having a 5 track HP cell for i4 a few questions came to mind. With i3 having HD libraries, as well as "denser" libraries across the board, what is the minimum number of tracks that one can achieve with a finFET without BPR? We know that 18A has the same minimum metal pitch as i4, so I don't think i3 is denser due to tighter metal pitch. The only other things that can be shrunk are cpp, M2 tracks, fewer fins, and further reductions to the n-p spacing. And even if you reduced n-p and fin count, wouldn't the number of tracks still need to be shrunk?

As an evolution of the above question what is the minimum number of M2 tracks for HNS? I think on this forum I have seen 5 with a BPR. Is this number different than it is for finFETs? If so, why? Shouldn't a HNS std cell should need the exact same amount of wiring for inputs and outputs as a finFET?
 
I get this. What I guess is harder for me to visualize is how you would scale below 5 M2 tracks without shrinking metal pitch. Even if you shrink n-p spacing, cpp, or number of fins the the std cell boundaries need to include the necessary wiring, no? Surely a std cell can't just be 2 M2 lines tall (even if your devices could somehow fit in this space), right? BPR/BSPDN can help, but i3 and the non BSPDN version(s) of N2 won't have this capability and likely won't/can't scale metal pitch to deliver their density improvements.
 
I get this. What I guess is harder for me to visualize is how you would scale below 5 M2 tracks without shrinking metal pitch. Even if you shrink n-p spacing, cpp, or number of fins the the std cell boundaries need to include the necessary wiring, no? Surely a std cell can't just be 2 M2 lines tall (even if your devices could somehow fit in this space), right? BPR/BSPDN can help, but i3 and the non BSPDN version(s) of N2 won't have this capability and likely won't/can't scale metal pitch to deliver their density improvements.
This is why actual cell utilisation compared to theory is lower than it used to be and is still dropping each node. BSPDN is a way to try and recover this, as well as improve PDN integruty.
 
My understanding is FinFETs can get to 5 tracks without BPR or backside power delivery, HNS need BPR or backside power delivery to get to 5 tracks. Forksheets can get HNS to around 4.3 tracks and there are some other routing tricks that can get HNS to 4 tracks. CFET can get below 4 tracks.
 
My understanding is FinFETs can get to 5 tracks without BPR or backside power delivery, HNS need BPR or backside power delivery to get to 5 tracks. Forksheets can get HNS to around 4.3 tracks and there are some other routing tricks that can get HNS to 4 tracks. CFET can get below 4 tracks.
Out of curiosity why does HNS need BPR to get to 5 tracks if finFETs can get there without it. In theory a HNS device can be as big as a 1 fin finFET, no? To say nothing of GF7 and i4 getting there with more than 2-3 fin devices.
 
Out of curiosity why does HNS need BPR to get to 5 tracks if finFETs can get there without it. In theory a HNS device can be as big as a 1 fin finFET, no? To say nothing of GF7 and i4 getting there with more than 2-3 fin devices.
I don't completely understand it myself, I will touch base with someone I know at Imec. I thought I had a general idea but I am not so sure now. By the way, what is GF7?
 
My bad I didn’t phase this well. GF 7 was GF’s 7LPP which if memory serves had a track number a touch above 5. I don’t know what fin count, but presumably it was 2 fins since single fin is a relatively new development with SS 7nm family and N3. i4 being the 3 fin device with 5 tracks. The 2-3 fin statement was GF and intel proving you could have 2 or 3 fins on sub 6 metal tracks. Sorry for the confusion
 
My bad I didn’t phase this well. GF 7 was GF’s 7LPP which if memory serves had a track number a touch above 5. I don’t know what fin count, but presumably it was 2 fins since single fin is a relatively new development with SS 7nm family and N3. i4 being the 3 fin device with 5 tracks. The 2-3 fin statement was GF and intel proving you could have 2 or 3 fins on sub 6 metal tracks. Sorry for the confusion
Yes i4 is 3 fins and 5 tracks, they really squeezed the cell boundaries and n-p spacing
 
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