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Mentor’s new Calibre Recon functionality methodically analyzes “early draft” IC designs for faster verification

Daniel Nenni

Admin
Staff member
Published May 29, 2019

Mentor, a Siemens business, today introduced Calibre Reconnaissance (“Recon”) functionality, representing the first of many new “easy button” features Mentor is adding to its Calibre™ platform IC physical verification portfolio to help design companies get to tapeout faster. The Calibre Recon functionality enables physical design and verification teams to rapidly perform physical verification for blocks and IC designs in their early development phase, when large counts of DRC errors are common, to methodically find and quickly fix selected classes of errors early in the IC design cycle. Now shipping with Mentor’s Calibre RealTime Digital platform and Calibre nmDRC tools, Calibre Recon helps companies streamline their design processes and speed time-to-market for demanding end-markets such as the IoT, AI, autonomous driving, and 5G communications spaces.

Early customers have experienced on average a 6x runtime improvement while requiring 4x less memory when analyzing early designs using Calibre Recon functionality. Calibre Recon accelerates debug cycles by showing only results associated with systemic issues common in early design development. The functionality provides designers with histograms, an SoC “heat map,” filtering/sorting capabilities, and other features that make it easier to quickly identify and address systemic issues. In addition, Calibre Recon is engineered to deliver all these capabilities from the very first run using any foundry/IDM Calibre sign-off design kits “as is,” and on any process technology node.

“Extending market and technology leadership in the EDA space requires constant improvement and deep understanding of the specific challenges customers face in their daily work,” said Michael Buehler-Garcia, vice president of Product Management for

Calibre Design Solutions at Mentor. “The introduction of Calibre Recon functionality underscores Mentor’s ongoing commitment to ensuring customers have the very latest technologies they need to quickly deliver world-class silicon products to market.”

Design engineers typically use the Calibre RealTime Digital tool alongside place and route software for successive layout refinements, while the Calibre nmDRC tool is used by physical verification engineers to perform meticulous batch-mode checks on entire blocks and chips. Instead of laying out their design and then running full-chip (batch) design rule checking (DRC) on “early draft” versions of their designs, users of the Calibre RealTime Digital and Calibre nmDRC tools can now leverage Calibre Recon functionality to help clean up these designs before they are run in full batch mode. This helps design teams shave hours, and in some customer experiences, even days off the IC verification process.

Using Calibre Recon functionality with the Calibre RealTime Digital tool

Design engineers can use the new Calibre Recon functionality in the Calibre RealTime Digital tool to find specific classes of errors for those areas in which initial design and layout is complete. Likewise, they can disable checks that are not useful at early stages (e.g. cells, blocks, macros) or layers of the design that are still works in progress. Calibre Recon gives designers complete control over which checks they want enabled and disabled, and which parts of the design they want checked. By running only specified DRC checks on the areas of the design where checking is needed, Calibre Recon helps designers avoid wasting unnecessary compute cycles on areas unrelated to the task at hand.

Using Calibre Recon functionality with the Calibre nmDRC tool

Calibre Recon functionality working with the Calibre nmDRC tool enables verification teams to implement a more methodical approach to running batch verification. For example, with extremely early designs, verification engineers can use the Calibre Recon functionality to find particular classes of errors across the entire chip, then assign specific design team members to fix these errors, speeding up the overall verification process. Similarly, they can use the Calibre Recon functionality to better inform place-and-route vendors and design teams of error creation, enabling them to refine their methods and/or tools.

The Calibre Recon functionality has been in use with select customers and is expected to be widely available in the 2019.3 release of the Calibre family update in June of 2019.

FOR MORE INFORMATION
Jack Taylor
jack_taylor@mentor.com
Mentor Graphics
512-560-7143

ABOUT MENTOR GRAPHICS
Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site: http://www.mentor.com.

Note: A list of relevant Siemens trademarks can be found here. Other trademarks belong to their respective owners.
 
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