[content] => 
    [params] => Array
            [0] => /forum/index.php?threads/lead-dft-engineer_allentown-pa.11651/

    [addOns] => Array
            [DL6/MLTP] => 13
            [Hampel/JobRunner] => 1030170
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000670
            [ThemeHouse/XPress] => 1010394
            [XF] => 2011072
            [XFI] => 1030270

    [wordpress] => /var/www/html

Lead DFT Engineer_Allentown, PA

Greetings from Eximius Design!

My name is Narayana and I am a manager handling USA recruitment efforts in Eximius Design.

Please go through the below job description and If you are qualified, available, planning to make a job change and have the required skills/qualifications and interest Kindly reply to me with your updated word format resume.

Seniority Level: Mid-Senior level
Industry: Semiconductors
Employment Type: Fulltime with Eximius and/or Contract(1099/CTC)
Job Area: Engineering – Hardware

Job Description:
• At least 8 years’ experience as a DFT Engineer within the semiconductor industry in a product development or R&D environment.
• Work comprises DFT verification for approximately 80 unique partitions
• Test-bench generation for all test-cases per validation test list to be specified (e.g. includes MBIST & Repair, Stuck-at, at-speed, cell-aware SCAN ATPG, internal proprietary tests for Intel 10nm DFT networks for TAP and other DFT infrastructure
• Simulation and debug of all tests (both standard Mentor tool test benches and custom Intel test benches
• Specification of ECO’s should a design fix be identified
• Pre-layout unit delay and post-layout unit delay, SDF-back-annotated simulations
• Tool flow and work environment utilizes Intel proprietary tool scripts and file formats. (Underlying tools for MBIST and SCAN are Tessent tools)
• Weekly report out of progress, metrics
• Translation of block level tests to SoC level; simulation at SoC level
• Simulation and debug of all tests (both standard Mentor tool test benches and custom Intel test benches)
• Weekly report out of progress, metrics
• Delivery to Intel Manufacturing Test Engineering (MPE)
• Provide pattern debug support to MPE, including failing pattern diagnosis, debug and regeneration of working patterns
• Debug of All Patterns for ATE (both for high-volume manufacturing and debug/diagnosis to production quality (i.e. addressing any and all marginality issues inherent in the patterns)
• Weekly report out of progress, metrics

If not interested, please be happy to share my contact with other talented design engineers and let’s connect and stay in touch

Happy to chat more if you have the time as well. Looking forward to hearing from you.

Thanks & Regards,

Lakshminarayana Parise
Eximius Design LLC