Intel now say they will be shipping 10nm server CPUs (Ice Lake SP) in 2H2020, not 2019 -- see roadmap above.
Interesting notes from the Intel Q2 2018 Call
- Thread starter Daniel Nenni
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Intel now say they will be shipping 10nm server CPUs (Ice Lake SP) in 2H2020, not 2019 -- see roadmap above.
Intel can't reduce their margins and undercut AMD prices because the yield on their huge monolithic server chips (~700mm2 ?) is much lower than the yield on AMDs multi-chip CPUs which have much smaller die (~200mm2 ?) -- there's simply no way they can win on price with their current approach.
And to answer Daniel, this is also why Intel can't just reduce margins to get 10nm 48C-64C server chips (which is what they need to compete with Rome) out of the door earlier, because the yields on such big die in 10nm would be ludicrously low (wafers per die instead of die per wafer?) and the manufacturing cost many times higher than their 14nm server CPUs which are their current cash cow -- they'd be massively reducing their margins by cannibalising their profitable 14nm server business with unprofitable (or even loss-making?) 10nm.
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I agree that AMD cannot write the big check today. What I am saying is that AMD has huge growth potential if their server chips are kept competitive with what Intel can offer.
Mobile is not growing, nVidia is already all TSMC, what other TSMC client has growth potential similar to AMD?
I do not know if TSMC would do that, but if I were them I would at least consider giving AMD some special treatment.
Lisa said that AMD will have the first 7nm GPU, beating Nvidia, so looks like AMD were able to write that big check!
Two things about that statement:
1) 2H 2019 is *very* late, certainly nothing to brag about.
2) I'm betting that it's only 4C products. 10nm will have much lower clocks than 14nm++, so enthusiast desktop chips will stay on 14nm++ until they can get 10nm to clock better.
Considering that AMD will launch 7nm Ryzen in 2Q/3Q 2019 and it will have 10% IPC improvement, that means AMD probably will have far better desktop chips than Intel for an entire year.
AMD is certainly a big upside for TSMC and I am sure they are more than accommodating. The question I have is which TSMC 7nm process will AMD use? The mobile SoC version or the HP version which is being developed with NVIDIA? The first GF 7nm is HP specifically for AMD.
That's a good point. For AMD the most important feature of TSMC 7nm, is that it's ready much earlier than Globalfoundries.
I think more is going on than just feeds and speeds here. That Risk Factor addition of security problems hurting competitiveness was not put there lightly. On the software side I hear of cloud guys re-writing code to get off INTC; they have lost trust. While silent, when history gets written I think Meltdown will be another straw that broke this camel's back. If only INTC shipped Meltdown chips it shows only they were taking certain chances in prefetch operations, possibly important enough to keep their lead. Without those gains, how much of their performance lead vanishes? I also wonder about those October BK stock sales. They look illegal to me. What ever happened, they wanted BK out of there FAST.
There isn't any fundamental difference between the TSMC (or GF) "SoC" and "HP" processes, for example with TSMC there's a 7FF process with many different options -- transistor Vth and voltage, number/thickness of metal layers (10-17?), capacitor options -- and then there are standard cell libraries with many options (9T, 7.5T, 6T, CPP57, CPP64) and different RAM libraries (high density, high speed) from various vendors (TSMC, Arm, Synopsys...). Most of these can be mixed and matched on the same chip depending on requirements and IP availability -- for example 9T/CPP57 or 7.5T/CPP64 libraries for high speed, 6T/CPP57 libraries for low power/high density. Then there are options like how the power grid is designed and decoupled which are really the next level up (how the libraries are used).
A process "developed with" or "specific to" a particular customer rarely means that the underlying process has been altered, this would have horrendous implications for PDK/supply/qualification. It usually just means that the particular choice of options and libraries has been done together with that customer and optimised for their application -- it's like having an "Nvidia cake" recipe which tastes really nice because of the particular way the ingredients are combined, anyone else has access to the same flour and butter and eggs but maybe they don't know how to put them together in the same delicious way or how to bake it.
For example, you can use "HP ingredients" (e.g. high metal layer count, thick top metal, ULVT transistors) and "SoC ingredients" (e.g. 6T libraries and high density RAMs) together if that happens to suit your application, or use completely different libraries for different blocks. There isn't even one standard "HP" or "SoC" process, within each of these categories there are different metal stacks available as well as other different options.
The only exception to this where there is a fundamental difference is DUV/EUV processes (e.g. TSMC 7FF and 7FF+) where there are real differences, and libraries are (usually) incompatible due to differences between DUV DP rules and EUV SP rules -- other differences may include new smaller low-power libraries for EUV (not just due to smaller metal pitch but also SDB/DDB and maybe 4.5T single-fin cells) to get even higher density where speed is less important.
But, in addition to all the available metal options etc., fundamental process differences between 7FF and 7HPC could be expected couldn't they, as has been the case at previous nodes? e.g thicker/ thinner gate oxides.
Yes of course. Apple pays a premium to get a process customized for their SoC designs. Saying they get the same process as others is incorrect. True it may be the same fab and equipment but the process recipe is different. And yes I am including the design interface (devices) in the "process" definition.
Ian
I understand what you are saying about no major difference between SoC and HPC flavors. Its basically one process with lots of options or knobs. But if we were to compare TSMC and GF processes I think there will be significant differences. I think Intel and GF seem to be the companies using cobalt for contacts and in their BEOL. Scotten even remarked that Intel and GF processes look more similar than different.
TSMC never gave much information about the MOL and BEOL changes in their 7nm process at IEDM 2016.
Chipworks >> Blog Archive >> IEDM 2016 – Setting the Stage for 7/5 nm
https://www.semiwiki.com/forum/content/6477-iedm-2016-7nm-shootout.html
Do you know more about the improvements ? GF gave quite a bit of details into the MOL and BEOL improvements in their IEDM 2017 paper. Scotten Jones and David Schor wrote in detail about the improvements
IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV – Page 3 – WikiChip Fuse
https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-versus-globalfoundries-leading-edge.html
Gary Patton stated that the biggest challenge in improving performance at 7nm and below is the at the contact and BEOL.
Semiconductor Engineering .:. The Race To 10/7nm
"Both the BEOL and MOL are critical. We can make the transistor faster and faster. But if we cannot supply the current and electrons in an efficient way to the transistor, we cannot harvest the benefits of the faster transistor," said Keyvan Kashefi, global product manager at Applied Materials. "As we move to 7nm, the delays and the performance become limited, mainly by the contact and back-end-of-line, because those become the bottleneck."
The interconnects - tiny copper wiring schemes in devices - are becoming more compact at each node, causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.
For the interconnects, chipmakers form a sea of tiny trenches, which are filled with conductive copper. Typically, the trenches are lined with a thin barrier layer (tantalum nitride) and a liner (tantalum). At each node, the liner/barrier film is taking up too much room and the volume of conductive copper is shrinking. So, some replaced tantalum with cobalt for the liner. "With cobalt, we significantly reduced the thickness of the liner," Kashefi said.
http://semiengineering.com/to-7nm-and-beyond/
Gary Patton
"But if you look at these advanced nodes, it's not so much about strain as parasitic resistances. The resistance getting into the device is the gate. The entire industry is going to cobalt on contacts as a key lever to improve resistance. We have a number of other knobs to improve resistance for back-end of line."
Tom Caulfield
"Devices used to focus on front-end of line. Now it has shifted to middle-of-line, because that's the gate. If you don't solve contact resistance, it doesn't matter what you do with devices. Once that's fixed, and you can make that as good as possible, then you have to go back to devices to get the next level of performance."
Recently we had an ARM fellow saying wire speed has stalled at 7nm.
https://www.eetindia.co.in/news/article/18060101-arm-aims-cortex-a76-at-high-performance-laptops
With its focus on small, low-power cores, Arm will get more benefit from next-generation process technologies than rival Intel, traditionally focused on driving up data rates. Arm claims that the latest 7-nm nodes will only deliver 2% to 3% more speed than the 16-nm node.
"There hasn't been much frequency benefit at all since 16 nm ... wire speed hasn't scaled for some time," said Peter Greenhalgh, an Arm fellow and vice president of technology.
Recent rumours of Apple A12 performance indicate that clocks are not scaling much at all.
http://www.iphonehacks.com/2018/07/geekbench-a12-chip-rumor.html
Somehow i am not sure that TSMC and GF processes are similar. GF has high perf customers like IBM and AMD whom they worked closely with when defining their 7nm node. I think Intel and GF have defined their processes with high performance requirements of their CPUs driving the process. The transistor level improvements do not have much meaning without the necessary MOL and BEOL improvements. I am hoping to hear what your thoughts are.
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AFAIK there is no difference in the fundamental transistor "recipe" for the "7nm" (which aren't, obviously...) core devices between "7SoC" and "7HP", there is only one core oxide thickness and minimum gate length for N7 (which is what TSMC call the basic process). There are features like rectangular contacts for lower resistance (at the expense of density) which *may* be used in "7HP" libraries (or may not...) but they're available in "7SoC" if you want to use them.
If Apple have a customised 7nm process, the customisation is much more likely to be in the libraries used or the I/O transistors (1.5V/1.8V/2.5V/3.3V) than the core transistors -- and of course they can have an "Apple custom" metal stack, but then so can anyone else if they're willing to pay for development and qualification of the libraries. And of course the process was likely to be designed around Apple's requirements anyway as the biggest customer...
This is all down to the confusion -- which is deliberately encouraged by some commentators -- between raw process (gates, transistors, contacts, MEOL, metal) and how it is used (libraries, metal options, contact options). An example is showing increased speed for "HP" compared to "SoC" when the only real differences are taller gate libraries with maybe different CPP (e.g. "high-speed" 7.5T 3-fin 64CPP compared to "high-density" 6T 2-fin 57CPP) -- all of which are options to be used as you choose.
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raghu78, I agree that the biggest issue with 7nm is transistor access resistance not the raw transistors themselves, especially the last connections down to the drain/source via MEOL which are very high resistance compared to older nodes. TSMC haven't published much detail of what they're doing here or what improvements have been made, but AFAIK TSMC and GF are pretty similar including their use (or not) of cobalt -- again, GF have been rather more open about this. For sure if you're trying to layout high-frequency custom circuits there are some very non-obvious ways to improve performance to help with access resistance and parasitic capacitance which would have seemed stupid in older nodes but help at 7nm.
My guess is that both have similar lists of process options and that you can actually build very similar chips in either process -- it may seem that TSMC are pushing "7SoC" and GF are pushing "7HP" because these are their most crucial markets (e.g. for Apple and AMD respectively), but certainly AMD have said that they can use whichever foundry best suits their requirements at the time and I'll bet there's no redesign involved here, which means there must be basic compatibility between the two processes.
My guess is that both have similar lists of process options and that you can actually build very similar chips in either process -- it may seem that TSMC are pushing "7SoC" and GF are pushing "7HP" because these are their most crucial markets (e.g. for Apple and AMD respectively), but certainly AMD have said that they can use whichever foundry best suits their requirements at the time and I'll bet there's no redesign involved here, which means there must be basic compatibility between the two processes.
Ian there is no confirmation from TSMC on the use of cobalt in N7 MOL and BEOL at IEDM 2016 or any technical conference whatsover. Moreover TSMC mentioned H300 and H360 cells at last year's TSMC symposium. But this year they only talked of H300 7.5T cells vs H240 6T in their comparisons. I remember you commenting that N7 CPP64 7.5T could have replaced N7 CPP57 9T. I asked Alex if N7 7.5T can deliver 4+ Ghz designs and he said he could not say.
2018
https://www.semiwiki.com/forum/content/7439-tsmc-technologies-mobile-hpc.html
2017
https://www.semiwiki.com/forum/content/6676-top-10-updates-tsmc-technology-symposium-part-ii.html
On the other hand we have GF saying that 7HPC can deliver 5 Ghz . We also saw 12LP 7.5T CPP=84nm match the speed of 14LPP 9T CPP=84nm at 16% lower power.
VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP – Page 3 – WikiChip Fuse
I had predicted that 12LP 7.5T will match the speed of 14LPP 9T when 12LP was announced last year.
Here are some details on GF 7SoC and GF 7HPC.
IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV – Page 4 – WikiChip Fuse
View attachment 22193
I think GF 7SoC 6T will deliver same speed as 12LP 7.5T and 14LPP 9T for lower power. I think 7HPC will allow AMD to deliver very high clocks on Ryzen 3000. fwiw my opinion is that Rome is at TSMC 7nm and Ryzen 3000 series at GF 7nm. I could be wrong. But this is what I expect. Moreover GF has confirmed they are taping out an AMD processor in H2 2018.
https://www.eetimes.com/document.asp?doc_id=1333326&page_number=2
Later this year, GF will use immersion steppers to tape out its first 7-nm chip, an AMD processor. An IBM processor will follow with ASICs coming in 2019, said Patton.
Intel and GF are the only companies confirmed to use cobalt in the MOL and BEOL. TSMC and Samsung have not confirmed the use of cobalt in MOL and BEOL at 7nm. Applied Materials confirms the same by saying some companies are using cobalt at 7nm. ARM says wire speed has not moved much at 7nm. fwiw ARM works closely with TSMC. Moreover TSMC is the only company in HVM at 7nm.
IEDM 2016 – Setting the Stage for 7/5 nm | Siliconica
https://fuse.wikichip.org/news/1479/vlsi-2018-samsungs-2nd-gen-7nm-euv-goes-hvm/5/
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On the AMAT call a question made the cobalt market seem small, at least for them. They were asked about cobalt use and customer success with integration and yield. Management got off the subject super quick by ignoring the customer success part and reciting an old statement that they got $70M in incremental business for one layer of cobalt and they expected $250-300M in incremental cobalt business in the next few years. That says to me no one is using cobalt, at least not theirs; the maths says four lines in a few years.
Intel and GF are using cobalt for contacts to reduce resistance and Intel is using cobalt for M0 and M1 though there are rumours that they might dump cobalt and go back to copper for M0 and M1. TSMC seems to have gone without cobalt for contacts and there are already claims of wire speed issues at TSMC N7. The statements by ARM are not encouraging. As Gary Patton of GF said the biggest challenge at the leading edge is perf and not density. Intel and GF cannot move to next gen process nodes without addressing the BEOL and MOL resistance as their process requirements are driven by high performance CPUs which clock around 5 Ghz. At 5nm TSMC is moving to cobalt. The question is " Are TSMC using cobalt for lowest metal layers at 5nm ?" I am sure cobalt will be used for contacts at TSMC 5nm. At 5nm via resistance becomes a bigger factor than line resistance and cobalt becomes a necessity.
https://nccavs-usergroups.avs.org/wp-content/uploads/Joint2017/NCCAVS-7-Besser-Talk-2_23_17.pdf
https://www.semiwiki.com/forum/cont...er-cobalt-ruthenium-interconnect-results.html
TSMC have been very cagey about whether they're using cobalt for contacts at 7nm; my guess is that they are for 7FF+ (as a pipecleaner for cobalt, like 7FF+ is for EUV, to get ready for 5nm), and are now using it for 7FF as well because they had to make some changes to the original 7FF process (retrofitted from 7FF+) to meet their speed targets. I don't know what they did, but improvements in access resistance were mentioned which makes me suspect cobalt -- of course there is no confirmation of this from TSMC.
You can also work backwards from the fact that several users (e.g. AMD) have said they expect to be able to choose between TSMC and GF for 7nm depending on timescale/volume requirements, which suggests the processes are pretty similar. If GF used cobalt (confirmed) and TSMC didn't then you wouldn't expect such direct porting to be possible, the higher contact resistance would give significant performance difference.
There are wire speed issues at 7nm full stop, not specific to TSMC -- if you connect great transistors with thin bits of wet string, what do you expect? This should be no surprise to anybody, the trend of interconnect delay increasing compared to gate delay is well known, it's the price you pay for high density with fine pitch low-level metal.
The way to help with this problem is to use a properly scaled metal stack with thicker and thicker layers above the bottom ones and use these for signals which have to travel further, but then this means fewer fine-pitch layers which reduces gate utilisation and therefore density and increases chip size -- so there's a tradeoff yet again between speed and density and cost.
This is often one of the biggest differences between "SoC" (lots of fine-pitch layers) and "HP" (fewer fine-pitch and more thick layers) processes -- along with gate height (number of tracks) and sometimes CPP.
Anyway, it's clear that 7nm isn't significantly faster than 10nm and you wouldn't expect this -- higher density (lower die cost for the same function) and lower power (for the same functionality) are the reasons people shift to 7nm. Or the chip just won't fit on a reticle or have reasonable yield, in other words pushing functionality up instead of area down.
You can also work backwards from the fact that several users (e.g. AMD) have said they expect to be able to choose between TSMC and GF for 7nm depending on timescale/volume requirements, which suggests the processes are pretty similar. If GF used cobalt (confirmed) and TSMC didn't then you wouldn't expect such direct porting to be possible, the higher contact resistance would give significant performance difference.
There are wire speed issues at 7nm full stop, not specific to TSMC -- if you connect great transistors with thin bits of wet string, what do you expect? This should be no surprise to anybody, the trend of interconnect delay increasing compared to gate delay is well known, it's the price you pay for high density with fine pitch low-level metal.
The way to help with this problem is to use a properly scaled metal stack with thicker and thicker layers above the bottom ones and use these for signals which have to travel further, but then this means fewer fine-pitch layers which reduces gate utilisation and therefore density and increases chip size -- so there's a tradeoff yet again between speed and density and cost.
This is often one of the biggest differences between "SoC" (lots of fine-pitch layers) and "HP" (fewer fine-pitch and more thick layers) processes -- along with gate height (number of tracks) and sometimes CPP.
Anyway, it's clear that 7nm isn't significantly faster than 10nm and you wouldn't expect this -- higher density (lower die cost for the same function) and lower power (for the same functionality) are the reasons people shift to 7nm. Or the chip just won't fit on a reticle or have reasonable yield, in other words pushing functionality up instead of area down.
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I think AMD has split their designs across TSMC and GF based on the process capabilities. My prediction is Rome is at TSMC 7nm while Ryzen is at GF 7nm. I also think Rome is using an interposer based design. There are rumours of AMD using a 8 (core dies)+1 (I/O die). This kind of design is practically not feasible without an interposer given that the majority of the power budget would be spent on moving data around if it was built on organic package. AMD is using TSMC's strengths - time to market advantage over Intel 10nm and foundry 7nm and advanced packaging to improve its competitive positioning in servers. For desktop they are using GF 7nm's high perf process which is designed for the best possible wire speed.
https://www.eetimes.com/document.asp?doc_id=1332049
To gear up for 7nm, "we had to literally double our efforts across foundry and design teams ... It's the toughest lift I've seen in a number of generations," perhaps back to the introduction of copper interconnects, said Mark Papermaster, in a wide-ranging interview with EE Times.
GF worked with IBM and AMD for over 2 years on 7nm node definition. TSMC's primary customers are in the mobile space with Apple, Qualcomm, Mediatek. TSMC does have high performance customers like Nvidia but they are not a designer of high perf CPUs.
As for your prediction that N7+ uses cobalt I think your statements are not consistent with what we are hearing about TSMC N7+. TSMC N7+ does not bring a perf improvement over N7. TSMC N7+ HPC brings a 10% perf improvment over N7+.
https://www.semiwiki.com/forum/content/7443-top-10-highlights-tsmc-2018-technology-symposium.html
I think TSMC 5nm will introduce cobalt atleast to contacts. The fact that TSMC N5 seems to have a HPC option indicates to me that the cobalt related changes will bring a good improvement in wire speed.
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