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Intel Meteor Lake delayed to the end of 2023

Why would it bother me? ;)
Yes, it could be the product itself is having problems. But then again it could be problem with the Intel 4 node. It's not unheard of to have yield problems on a new node.

Remember, Intel 4 is not a full node, it only produces CPU chiplets. Intel 3 is the full node that will fab full chips for others. If Intel can't produce chiplets with 4 then 3 is going to be a real challenge. My sources say Intel 4 yield is fine and the Intel 3 PDKs are good. My sources also say that Intel 18A is doing very well and will most likely lead the GAA era. TSMC is definitely up for the challenge but Samsung will have more difficulties, just my opinion of course.
 
Remember, Intel 4 is not a full node, it only produces CPU chiplets. Intel 3 is the full node that will fab full chips for others. If Intel can't produce chiplets with 4 then 3 is going to be a real challenge. My sources say Intel 4 yield is fine and the Intel 3 PDKs are good. My sources also say that Intel 18A is doing very well and will most likely lead the GAA era. TSMC is definitely up for the challenge but Samsung will have more difficulties, just my opinion of course.
A little bit of confused here. I recall Intel 4 (1st EUV adaption) and Intel 20A (1st GAA) are the full nodes that these are the nodes which make the major technical leaps. Intel 3 and Intel 18A make some minor process changes from 4/20A so they are half nodes. Are these right?
 
A little bit of confused here. I recall Intel 4 (1st EUV adaption) and Intel 20A (1st GAA) are the full nodes that these are the nodes which make the major technical leaps. Intel 3 and Intel 18A make some minor process changes from 4/20A so they are half nodes. Are these right?
Its more like Intel 4 and 20A are the half nodes, as they are chiplet nodes without the full node PDKs. Intel 3 and 18A involve minor changes that offer some increase in performance but have the full PDK. Intel 4 and 20A introduce the new technology, but on a smaller scale. To me it seems like a Tick-Tock strategy where Intel first tries the new technology on a chiplet node, and then expands it to the full node.
 
The author Dylan Patel added a comment on his Twitter:
"MTL-P is what's being talked about in the report.
Both U and H are even later than that date.
None is talking about S here."
I'm getting very confused as to what he's trying to claim except that he thinks MTL will be delayed (as Intel almost always does). Although everyone has good reason to doubt that Intel can actually deliver on time, I haven't seen many murmurs of MTL basically being almost delayed to Q1 2024. Might end up actually happening but I'm not so sure he has actual "sources" and think that he's just throwing it out there because he think its a pretty safe bet that Intel is delayed. If he really is faking it, it makes sense for him to do this.
 
I got the impression that Intel 4 and 20A are only there to make it appear that Intel is releasing a new node every year. Intel 4 seems to be pointless to me. Granite Rapids has already moved to Intel 3. Meteor Lake is only 25% Intel 4 and it's only laptop. The desktop product has been replace by Raptor lake refresh.
 
I got the impression that Intel 4 and 20A are only there to make it appear that Intel is releasing a new node every year. Intel 4 seems to be pointless to me. Granite Rapids has already moved to Intel 3. Meteor Lake is only 25% Intel 4 and it's only laptop. The desktop product has been replace by Raptor lake refresh.

Since Intel 4 only does chiplets it is not a complete node by my definition. No IOs etc..... It really is a pipe cleaner process, which is why I don't believe there are process problems with Intel 4. Doing chiplets and doing complex SoCs (Apple, Nvidia, QCOM) are a completely different challenge.

I think Intel is doing the right thing here, it is called yield learning and TSMC does this quite well with N7, N7+, N6 etc... but they are not full nodes. In fact, I think calling them half nodes is being generous.
 
There is some confusion with the term "half node", "full node". Full node used be mean a full optical shrink and a "half node" used mean it would have roughly the same pitches as the full node, but with small tweaks (i.e. less tracks, etc.)
"half node" is now being used to mean a node with an incomplete cell library (ie. Intel 4, has no high density library). I believe N6, N7+ have full cell libraries, but the pitches are about the same as their parent node N7.
 
There is some confusion with the term "half node", "full node". Full node used be mean a full optical shrink and a "half node" used mean it would have roughly the same pitches as the full node, but with small tweaks (i.e. less tracks, etc.)
"half node" is now being used to mean a node with an incomplete cell library (ie. Intel 4, has no high density library). I believe N6, N7+ have full cell libraries, but the pitches are about the same as their parent node N7.
Thanks to point out the difference. Previously the definitions I realized in books/internet/work environment are the former you mentioned.
 
There is some confusion with the term "half node", "full node". Full node used be mean a full optical shrink and a "half node" used mean it would have roughly the same pitches as the full node, but with small tweaks (i.e. less tracks, etc.)
"half node" is now being used to mean a node with an incomplete cell library (ie. Intel 4, has no high density library). I believe N6, N7+ have full cell libraries, but the pitches are about the same as their parent node N7.

Correct, we are packaging new technology into old terminology.

At one time we called an optical shrink a half node. For example, we shrunk a high volume GPU from 65nm down to 55nm for a high volume customer.

 
I got the impression that Intel 4 and 20A are only there to make it appear that Intel is releasing a new node every year. Intel 4 seems to be pointless to me. Granite Rapids has already moved to Intel 3. Meteor Lake is only 25% Intel 4 and it's only laptop. The desktop product has been replace by Raptor lake refresh.
Okay so what would MTL use if they axed intel 4? Get delayed 6 months for intel 3 or N3E, or launch at the same time with N3 and cost more and have worse performance? As Dan also said intel 4 is an important yield learning step for intel 3. MTL is also a simpler product to debug than a full chip with all of the different libraries that would be required. Ramping MTL on intel 4 this year should also allow for a trivial ramp of intel 3 (relative to ramping a brand "new node" anyways).

Since Intel 4 only does chiplets it is not a complete node by my definition. No IOs etc..... It really is a pipe cleaner process, which is why I don't believe there are process problems with Intel 4. Doing chiplets and doing complex SoCs (Apple, Nvidia, QCOM) are a completely different challenge.
I would agree. Comparing intel 4 to say N3E in argrigate isn't a total apple to apple comparison. Although given the technological similarity to intel 3 there is still some merit to comparing the various technical aspects of these nodes (even if the nodes as a whole aren't directly comparable). Given TSMC's model of just bringing out only the IP that Apple needs on the initial versions of their new full nodes (N7, N5, N3) I would say intel 4 to the base versions of N3 or N5 are closer to being apples to apples comparisons. I do disagree with you on your comment of doing chiplets vs SOCs being harder than the node. If we ignore the denser HP libraries and 18% PPW on intel 3 and just talk about enabling the rest of the PDK, I can't imagine that all of the care that went into making intel 4 is harder than finally getting around to validating those HD library DRs and adding io fins.

Public data seems to confirm this. I think Murphy made some comments in like 2018 (or something like that) about how 7nm moved to a parallel development model with 10nm so that 7nm wouldn't be delayed. He also said the intent was to have a 2 year cadence with reduced targets instead of the 3 years and 2.7x density they were aiming for with 10nm. Latter on intel would go onto say they would launch 7nm products in 2021 (funnily enough if memory serves me right, I think this was supposed to be their graphics products). Now we will see "7nm" products launching in 2023. Meanwhile 3-4 quarters after intel 4 reached HVM readiness we will see intel 3 reach readiness with the full PDK enabled and a bunch of enhancments. This timeline of events doesn't add up for full chips/PDKs to be much harder than coming up with the base skeleton node.

I think calling them half nodes is being generous.
On a density front you are totally right. Performance wise I think calling them half-nodes is to do them a diservcice. When one looks at N4P vs N3 PPW is similar despite the large lithographic shrink (at least by the standards of the era where those kinds of shrinks are very hard). Heck in 3-4 quarters intel 3 is supposed to be almost as a big of a jump over intel 4 as intel 4 was over intel 7. Long story short I don't think we should discount the massive improvements that are being made to these nodes of their lifetimes just because the cost per transistor for these nodelets is more or less flat.
 
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TSMC N4, seeing as 75% of it is already on that node ;)
No, it isn’t. Why would intel put the io and soc tiles on N4P AMD and intel have always diagrigated these sorts of functions onto older nodes. And if they did put the compute tile on N4P intel would have to take a large density penalty to have the privilege of having a weaker node that uses more power and slowing down the yield learning they need for their server products and trailing edge customers.
 
The thing about chiplets is putting them all together is a very difficult thing. If I were to bet on the reason for a chip delay it would the integration of chiplets. Chiplets, easy to say but much harder to do.
Architecture/Simulation or manufacturing?
 
Architecture/Simulation or manufacturing?

Simulation for sure. Manufacturing maybe. Getting the chiplets to work together is going to be a challenge, especially if you did not design them. Intel, AMD, Nvidia, etc will all make their own chiplets so it should be easier.. It really is early for chiplets so we don't know what we don't know. Just ask Intel. ;)
 
The first product on Intel 4 is Meteor Lake. If Meteor lake is delayed. Then Intel 4 is delayed. EUV volume learning is delayed. Product or process ... I am sure Intel people are arguing about that internally as well. When will we see a PC with meteor lake that we can buy? I don't care if it is "HVM ready", "in production", "launched", or "Ready to ship"... we know these are vague terms used for PR. When will we see a PC based on meteor lake for order?

IMO: if the information is correct, I don't care about the personal background of the source. Both David and Dylan have excellent information .... always check your other sources to confirm their information as accurate. we already did. Just an opinion
 
The first product on Intel 4 is Meteor Lake. If Meteor lake is delayed. Then Intel 4 is delayed. EUV volume learning is delayed. Product or process ... I am sure Intel people are arguing about that internally as well. When will we see a PC with meteor lake that we can buy? I don't care if it is "HVM ready", "in production", "launched", or "Ready to ship"... we know these are vague terms used for PR. When will we see a PC based on meteor lake for order?
There is a SiFive board on Intel 4, supposedly to launch this summer using Horse Creek. Might be out earlier than MTL.
 
The first product on Intel 4 is Meteor Lake. If Meteor lake is delayed. Then Intel 4 is delayed. EUV volume learning is delayed. Product or process ... I am sure Intel people are arguing about that internally as well. When will we see a PC with meteor lake that we can buy? I don't care if it is "HVM ready", "in production", "launched", or "Ready to ship"... we know these are vague terms used for PR. When will we see a PC based on meteor lake for order?

If Meteor lake is delayed. Then Intel 4 is delayed. EUV volume learning is delayed.

First of all this assumption is false. If any one of the chiplets is delayed the chip is delayed and as I said before assembling a multi die chip is a challenge in itself. There was no mention of Intel 4 EUV problems at SPIE last week. Intel did talk about 18A EUV and beyond. I was told last December that Intel 4 EUV was fine. I will ask again but I highly doubt that the EUV status has changed for the worst.
 
First of all this assumption is false. If any one of the chiplets is delayed the chip is delayed and as I said before assembling a multi die chip is a challenge in itself. There was no mention of Intel 4 EUV problems at SPIE last week. Intel did talk about 18A EUV and beyond. I was told last December that Intel 4 EUV was fine. I will ask again but I highly doubt that the EUV status has changed for the worst.
I think the “press” is confusing everyone because it looks like Intel may have removed or somewhat de-scoped Meteor Lake-S (desktop) from the roadmap, replacing with Raptor Lake refresh. They’re taking the leap that “no desktop MTL means Intel 4 is bad” and inferring a slip on the mobile MTL.

I’m pretty sure the changes to the desktop roadmap are more to do with node capacity than yields, especially as these nodes are going to be iterated very quickly.
 
I think the “press” is confusing everyone because it looks like Intel may have removed or somewhat de-scoped Meteor Lake-S (desktop) from the roadmap, replacing with Raptor Lake refresh. They’re taking the leap that “no desktop MTL means Intel 4 is bad” and inferring a slip on the mobile MTL.

I’m pretty sure the changes to the desktop roadmap are more to do with node capacity than yields, especially as these nodes are going to be iterated very quickly.
Intel knew their Intel 4 capacity 1-2 years ago.
Could be lack of confidence of their yield in future MP.
 
IMO: if the information is correct, I don't care about the personal background of the source. Both David and Dylan have excellent information .... always check your other sources to confirm their information as accurate. we already did. Just an opinion

As it turns out this information is not correct so keep that in mind the next time an alarmist with no semiconductor experience publishes something provocative in a shameless click grab.
 
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