Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/intel-_does_-read-semiwiki.13990/page-2
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Intel _does_ read Semiwiki!

"So tell me how a slightly larger die size chip consumes less power?".
I think it's possible - depends on a number of factors. The libraries are almost certainly different - the 16 TSMC library might be lower power (or faster at the same power) than the Samsung 14nm used in some important details. Also possible that leakage might be different. It also depends what we mean by "ported". If this is a fresh synthesis and layout on the new process/libraries, then you're also at the mercy of the designers and tools - it may be the design implementation in one case was better than the other. Not saying any of these are the case - but such things are possible. 5-10% smaller die area might not always mean lower dynamic/leakage/total power.

This was a GDS to GDS port. Some call it a migration. No synthesis was involved. This was a very time sensitive operation. Millions of die were at stake.
 
This was a GDS to GDS port. Some call it a migration. No synthesis was involved. This was a very time sensitive operation. Millions of die were at stake.
Is it even possible on any much recent nodes? I believe process differences are most dramatic.
 
So tell me how a slightly larger die size chip consumes less power?
Did you go through the link you posted? The video in that link literally claimed extra power drain from the A9 fabricated using Samsung’s 14nm node. Regarding the larger die size consuming less power, Samsung’s 14LPE suffered more from leakage due to the material they deployed for as they leaped directly from their 28nm node to their 14LPE because they lost the A8 chip orders to TSM. This resulted in higher power dissipation and significant overheating issues.
 
Did you go through the link you posted? The video in that link literally claimed extra power drain from the A9 fabricated using Samsung’s 14nm node. Regarding the larger die size consuming less power, Samsung’s 14LPE suffered more from leakage due to the material they deployed for as they leaped directly from their 28nm node to their 14LPE because they lost the A8 chip orders to TSM. This resulted in higher power dissipation and significant overheating issues.

No, I did not watch the video. I'm sorry but a 2 hour battery difference is not believable, leakage or not. My 6s had a TSMC chip and I talked to others with TSMC and Samsung chips and did not discover a noticeable difference. One thing I can tell you is that the iPhone 6s did not have great battery life with either chip.
 
No, I did not watch the video. I'm sorry but a 2 hour battery difference is not believable, leakage or not.
Here’s the 2 hour difference that caused a big deal back then.
This happened really long ago so I understand you don’t remember all the details. A quick google search, however, would have saved you from all this hassle. All the best!!
 
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Here’s the 2 hour difference that caused a big deal back then.
This happened really long ago so I understand you don’t remember all the details. A quick google search, however, would have saved you from all this hassle. All the best!!

Sorry, I did not know the source was an anonymous benchmark post on Reddit. I stand corrected. I wonder why the Samsung phone had a SIM card and the Apple did not? Weird.
 
Sorry, I did not know the source was an anonymous benchmark post on Reddit. I stand corrected. I wonder why the Samsung phone had a SIM card and the Apple did not? Weird.
Your reply citing the Chipgate article features an Austin Evans’s video showing that he calibrated both screens at 200nits and ran a geekbench 3 battery test to 50% battery. The TSM one lasted 50 extra minutes. So yeah, I would believe a full drain test would be close to 100 minutes as shown in the anonymous post on reddit.


I have also marked the time for you on YouTube.
Best Regards.
 
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