While the PCIe 6.0 specification is expected to be finalized and released later in 2021, PLDA has been hard at work to address the needs of early adopters looking for the most advanced PCIe 6.0 IP solution for their SoCs and ASICs.
Although PCIe 5.0-enabled systems are not yet available in the general market, Automotive, AI and IoT system designers are already pushing for more bandwidth than 5.0 supports.
At PLDA, we develop leading edge high-speed interfaces, with a strong development focus on PCIe. While PCIe is found in many applications, and can be delivered “off the shelf”, PCIe can become “strategic” and highly sensitive in high-end use cases. With the latest PCIe specifications, a growing number of features associated with an exponential quantity of verification tests mean that IP development has become more and more complex. This level of complexity requires a dedicated team working together, focused on delivering high quality, high performance, reliable IP.
As the PCIe 6.0 specification advances towards finalization, PLDA is designing its XpressRICH for PCIe 6.0 controller IP. Today, we are pleased to announce that this IP will support the following features:
- Backwards compatibility to PCIe 1.1
- Fully parameterized
- Native Tx/Rx or TLP user interface
- PIPE LPC and SerDes mode
- Same RTL for ASIC and FPGA implementation
contact us to align roadmaps and discuss requirements.[/TD]