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IMEC predicts Nanosheets do not help SRAM scaling, advocates forksheets for limited (-6%) scaling

Fred Chen


SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM.
To be expected since as the article states, HD sram uses single fin devices. If HNS reduce SRAM area it has to be with the reduced cpp that should hopefully happen on N1.4 and SF2/1.4. It also makes a man wonder if when TSMC talks about >15% logic scaling for N2 if, 15% is the HD finflex -> HD scaling and the greater than refers to HP scaling. I do also wonder if the larger scaling that I expect N3e->N2 will have for HCC sram and HP logic will lead to greater use of these libraries by designers due to the areal cost malices of these libraries pressumbly being less than it is for finfets.