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IBM Unveils World's First 2 Nanometer Chip Technology

Daniel Nenni

Admin
Staff member
New chip milestone to propel major leaps forward in performance and energy efficiency
  • ALBANY, N.Y., May 6, 2021 /PRNewswire/ -- IBM (NYSE: IBM) today unveiled a breakthrough in semiconductor design and process with the development of the world's first chip announced with 2 nanometer (nm) nanosheet technology. Semiconductors play critical roles in everything from computing, to appliances, to communication devices, transportation systems, and critical infrastructure.

    "The IBM innovation reflected in this new 2 nm chip is essential to the entire semiconductor and IT industry."
    Demand for increased chip performance and energy efficiency continues to rise, especially in the era of hybrid cloud, AI, and the Internet of Things. IBM's new 2 nm chip technology helps advance the state-of-the-art in the semiconductor industry, addressing this growing demand. It is projected to achieve 45 percent higher performance, or 75 percent lower energy use, than today's most advanced 7 nm node chipsi.
    • IBM_Research_2_nm_Wafer.jpg


    • IBM Research 2 nm Wafer
    • IBM_Research_2_nm.jpg


    • IBM Research 2 nm
    • IBM_Research_Albany_Exterior_1.jpg


    • IBM Research Albany Exterior 1
    • 2 nm chip technology video


    • 2 nm chip technology video
    • Row_of_2_nm_nanosheet_devices.jpg


    • Row of 2 nm nanosheet devices
    • IBM_Research_2_nm_Wafer.jpg


    • IBM Research 2 nm Wafer
    • IBM_Research_2_nm.jpg


    • IBM Research 2 nm
    • IBM_Research_Albany_Exterior_1.jpg


    • IBM Research Albany Exterior 1
    • 2 nm chip technology video


    • 2 nm chip technology video
    • Row_of_2_nm_nanosheet_devices.jpg


    • Row of 2 nm nanosheet devices
    • IBM_Research_2_nm_Wafer.jpg


    • IBM Research 2 nm Wafer
    • IBM_Research_2_nm.jpg


    • IBM Research 2 nm
    • IBM_Research_Albany_Exterior_1.jpg

      IBM Research Albany
    The potential benefits of these advanced 2 nm chips could include:
    • Quadrupling cell phone battery life, only requiring users to charge their devices every four daysii.
    • Slashing the carbon footprint of data centers, which account for one percent of global energy useiii. Changing all of their servers to 2 nm-based processors could potentially reduce that number significantly.
    • Drastically speeding up a laptop's functions, ranging from quicker processing in applications, to assisting in language translation more easily, to faster internet access.
    • Contributing to faster object detection and reaction time in autonomous vehicles like self-driving cars.

  • "The IBM innovation reflected in this new 2 nm chip is essential to the entire semiconductor and IT industry," said Darío Gil, SVP and Director of IBM Research. "It is the product of IBM's approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D ecosystem approach."

    IBM at the forefront of semiconductor innovation
    This latest breakthrough builds on decades of IBM leadership in semiconductor innovation. The company's semiconductor development efforts are based at its research lab located at the Albany Nanotech Complex in Albany, NY, where IBM scientists work in close collaboration with public and private sector partners to push the boundaries of logic scaling and semiconductor capabilities.

    This collaborative approach to innovation makes IBM Research Albany a world-leading ecosystem for semiconductor research and creates a strong innovation pipeline, helping to address manufacturing demands and accelerate the growth of the global chip industry.

    IBM's legacy of semiconductor breakthroughs also includes the first implementation of 7 nm and 5 nm process technologies, single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, Silicon on Insulator technology, multi core microprocessors, High-k gate dielectrics, embedded DRAM, and 3D chip stacking. IBM's first commercialized offering including IBM Research 7 nm advancements will debut later this year in IBM POWER10-based IBM Power Systems.

    50 billion transistors on a fingernail-sized chip
    Increasing the number of transistors per chip can make them smaller, faster, more reliable, and more efficient. The 2 nm design demonstrates the advanced scaling of semiconductors using IBM's nanosheet technology. Its architecture is an industry first. Developed less than four years after IBM announced its milestone 5 nm design, this latest breakthrough will allow the 2 nm chip to fit up to 50 billion transistors on a chip the size of a fingernail.

    More transistors on a chip also means processor designers have more options to infuse core-level innovations to improve capabilities for leading edge workloads like AI and cloud computing, as well as new pathways for hardware-enforced security and encryption. IBM is already implementing other innovative core-level enhancements in the latest generations of IBM hardware, like IBM POWER10 and IBM z15.

    About IBM
    IBM is a leading global hybrid cloud and AI, and business services provider, helping clients in more than 175 countries capitalize on insights from their data, streamline business processes, reduce costs and gain the competitive edge in their industries. Nearly 3,000 government and corporate entities in critical infrastructure areas such as financial services, telecommunications and healthcare rely on IBM's hybrid cloud platform and Red Hat OpenShift to affect their digital transformations quickly, efficiently, and securely. IBM's breakthrough innovations in AI, quantum computing, industry-specific cloud solutions and business services deliver open and flexible options to our clients. All of this is backed by IBM's legendary commitment to trust, transparency, responsibility, inclusivity, and service.

    For more information, visit www.ibm.com

    Media Contacts
    Bethany Hill McCarthy, bethany@ibm.com
    IBM Research

    Sam Ponedal, sponeda@us.ibm.com
    IBM Cognitive Systems

    i Based on the projected industry standard scaling roadmap
    ii Based on current usage statistics for 7 nm-based cell phones
    iii https://science.sciencemag.org/content/367/6481/984



    SOURCE IBM
 
The die size looks like 25 mm x 32 mm or 800 mm2. 50 billion transistors gives 62.5 million transistors/mm2.

IBM_Research_2_nm_Wafer.jpg

IBM_Research_2_nm.jpg
 
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Scotten Jones has an analysis on this to be published on Sunday morning and he speaks from experience.

Spoiler alert:

After analyzing the IBM announcement, we believe their “2nm” process is more like a 3nm TSMC process from a density perspective with better power but inferior performance. The IBM announcement is impressive but is a research device that only has a clear benefit versus TSMC’s 3nm process for power and TSMC 3nm will be in risk starts later this year and production next year. We further believe that TSMC will have the leadership position in density, power, and performance at 2nm when their process enters production around 2023/2024.
 
How does that compare to Samsung 3nm and TSMC 3nm?

If you remember back when IBM did similar announcements at 7nm and 5nm you will see that this is a lab experiment that never went into production. So to me this is a very shallow announcement.
62.5 Mtr/mm2 is lower density than TSMC N7 on a variety of smartphones. It shouldn't be their highlight. It would be more of a concern that the gate pitch is not reduced so much.

Update: It is not in the announcement, but 150 mm2 taken as fingernail size would give 333 Mtr/mm2. Then the actual chip would be 267 billion transistors, which would be worth announcing, maybe more so than the 50 billion number.
 
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Scotten Jones has an analysis on this to be published on Sunday morning and he speaks from experience.

Spoiler alert:

After analyzing the IBM announcement, we believe their “2nm” process is more like a 3nm TSMC process from a density perspective with better power but inferior performance. The IBM announcement is impressive but is a research device that only has a clear benefit versus TSMC’s 3nm process for power and TSMC 3nm will be in risk starts later this year and production next year. We further believe that TSMC will have the leadership position in density, power, and performance at 2nm when their process enters production around 2023/2024.
This is just one example of why I come and read (and listen to Daniel's podcasts) Semiwiki.com.

The content/information here is just top notch. The site is intuitive and the community is incredibly smart, diverse and (generally) friendly. Well done, Mr. Nenni(s)....best wishes on the site's continued growth!
 
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