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For lower nodes like 10nm and 7nm , foundries are using SADP process for processing of Mx layers . I would like to know what is the approach
using by tsmc/samsung/intel for these SADP layers ?
The various approaches are 1. Traditional SID-SADP (Block Mask) 2. Mandrel Fill/Cut Mask SID-SADP 3. SIM SADP .
Chances are the foundries could start with LE3 for this year's newest nodes, but GlobalFoundries did publish an SPIE 2017 paper (Exploiting Regularity: Breakthroughs in Sub-7nm Place-and-Route) where they could design SAQP-friendly layouts, i.e., one (193i) cut mask at metal level. IMEC also has a paper (Low Track Height Standard cell Design in iN7 using Scaling Boosters) on low track height (6 and 6.5 track) cells, which are SAQP-friendly.
